Increase in the scattering of electric field lines in a new high voltage SOI MESFET

Anvarifard, Mohammad K.

doi:10.1016/j.spmi.2016.06.005

Cited by 24 publications

(5 citation statements)

References 29 publications

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“…LDMOS (laterally double diffused MOSFET) and SOI LDMOS have high input impedance. They are widely used in high frequency application 1–4 . However, due to the technological restriction the breakdown voltage of the device is limited.…”

Section: Introductionmentioning

confidence: 99%

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Reduction in area‐specific on‐resistance with vertical stepped doped high‐kVDMOS

Parmar

Gupta

2021

Int J Numerical Modelling

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In this article, a novel high-k VDMOS with vertical stepped doping profile is presented. It possesses lower area specific on-resistance (R on A) in comparing to the conventional structure while the blocking capacity remains unaltered. Hence, the trade-off between the breakdown voltage and R on A is optimized as well as area specific on-resistance is reduced from 68% to 27%. The proposed structure shows analogous behavior as conventional structure with improved current driving capability from 42% to 24%. Thus, it exhibits improved device characteristics and possesses enhanced figure of merits than conventional structure.

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Section: Introductionmentioning

confidence: 99%

“…They are widely used in high frequency application. [1][2][3][4] However, due to the technological restriction the breakdown voltage of the device is limited. The desire for high breakdown voltage gave birth to VDMOS.…”

mentioning

confidence: 99%

Reduction in area‐specific on‐resistance with vertical stepped doped high‐kVDMOS

Parmar

Gupta

2021

Int J Numerical Modelling

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“…To solve this problem, scientists have proposed many new structures [4][5][6][7][8]. SOI technology is introduced into SJ LDMOS with its advantages of ideal dielectric isolation and relatively simple dielectric isolation process [9][10][11][12][13]. However, SOI has a low vertical BV, which hinders its development.…”

Section: Introductionmentioning

confidence: 99%

PSJ LDMOS with a VK dielectric layer

Lei

et al. 2019

Micro & Nano Letters

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A partial super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with a variable-k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low-k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance (R on,sp). Furthermore, according to an enhanced dielectric layer field, low-k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the 'silicon limit' at the same BV class, which breaks the 'silicon limit'.

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“…Utilizing the silicon‐on‐insulator technology is an interesting solution to improve the short channel effects and electrical performance for the nanoscale devices owing to high immunity to latch‐up current, smaller parasitic capacitance, and high transconductance . The importance of SOI technology is so high that many papers are attributed to it for both low‐voltage and high‐voltage cases …”

Section: Introductionmentioning

confidence: 99%

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

Anvarifard

2018

Int J Numerical Modelling

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Silicon-on-insulator junctionless transistor (SOI-JLT) is introduced as an efficient device for nanoscale destinations. Moreover, critical lattice temperature and high leakage current are taken into account as the fundamental challenges can limit the use of the SOI-JLTs. This paper aims to modify a conventional junctionless in order to improve the electrical and thermal performance. A new window filled by lightly doped P-type silicon material opens inside a part of the buried oxide beneath the channel region. This reformation in the junctionless creates a depletion layer at the channel region/new window interface to reduce the leakage current, successfully. Also, the critical lattice temperature of the proposed structure will be mitigated owing to higher effective thermal conduction in contrast to the conventional SOI-JLT structure. Two carriers and two-dimensional (2D) simulation of the structures under the study considering the various spectra of parameters in terms of lattice temperature, leakage current, electron temperature, driving current, transconductance, output conductance, parasitic capacitance, current gain, unilateral power gain, cutoff frequency, maximum oscillation frequency, and minimum noise figure revealed that the suggested device provides a better opportunity for the researchers and experimentalists to implement and develop it for VLSI applications.KEYWORDS depletion layer, electrical performance, junctionless, silicon-on-insulator, temperature lattice | INTRODUCTIONUtilizing the silicon-on-insulator technology is an interesting solution to improve the short channel effects and electrical performance for the nanoscale devices owing to high immunity to latch-up current, smaller parasitic capacitance, and high transconductance. 1-3 The importance of SOI technology is so high that many papers are attributed to it for both low-voltage and high-voltage cases. [4][5][6][7][8][9][10][11][12][13][14][15] The nanoscale junctionless is welcomed to VLSI industry since it overcomes the basic weaknesses of SOI-MOSFETs. The most important factor to limit using the nanoscale SOI-MOSFET structures is that they need a very sharp and step doping profile keeping the SOI technology advantages which is very hard and sometimes impossible due to technological challenges of the MOSFET-based devices. 16 The advent of the junctionless structure has given a new sprit to the VLSI industry since it is very compatible with the conventional MOSFET fabrication process along with promoted electrical performance. 17,18 It is the importance of

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Increase in the scattering of electric field lines in a new high voltage SOI MESFET

Cited by 24 publications

References 29 publications

Reduction in area‐specific on‐resistance with vertical stepped doped high‐kVDMOS

Reduction in area‐specific on‐resistance with vertical stepped doped high‐kVDMOS

PSJ LDMOS with a VK dielectric layer

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

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