Increasing the Applicability of Scalar Replacement

Abstract. Software Transactional Memory (STM) compilers commonly instrument memory accesses by transforming them into calls to STM library functions. Done naïvely, this instrumentation imposes a large overhead, slowing down the transaction execution. Many compiler optimizations have been proposed in an attempt to lower this overhead. In this paper we attempt to drive the STM overhead lower by discovering sources of sub-optimal instrumentation, and providing optimizations to eliminate them. The sources are: (1) redundant reads of memory locations which have been read before, (2) redundant writes to memory locations which will be subsequently written to, (3) redundant writeset lookups of memory locations which have not been written to, and (4) redundant writeset record-keeping for memory locations which will not be read. We describe how static analysis and code motion algorithms can detect these sources, and enable compile-time optimizations that signicantly reduce the instrumentation overhead in many common cases. We implement the optimizations over a TL2 Java-based STM system, and demonstrate the eectiveness of the optimizations on various benchmarks, measuring up to 29-50% speedup in a single-threaded run, and up to 19% increased throughput in a 32-threads run.

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“…Scalar promotion, which eliminates redundant memory writes, was introduced by Lu and Cooper [17], and improved by later works (e.g. [21]). …”

Section: Discussionmentioning

confidence: 99%

Lowering STM Overhead with Static Analysis

Afek

Korland

Zilberstein

2011

Languages and Compilers for Parallel Computing

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“…Most of the work has focused on high-end computing and has thus ignored the issue of precise data accesses. So and Hall (2005) have extended the work by Carr and Kennedy (1999) for scalar replacement targeting FPGAs. They focus on identifying the number of accesses during a given computation by analysis of the arrays index subscript functions.…”

Section: Related Workmentioning

confidence: 95%

“…, d n >, where d i is a constant, a 'þ' (all positive) or *(unknown). The distance vector usually represented as a form of directed graph, called a reuse chain (So and Hall 2005). Details of the analysis to determine reuse vectors and distance vectors for single-induction-variable (SIV) and multiple induction variables (MIV) are described (Baradaran et al 2005).…”

Section: Data Reuse Analysis and Reuse Vectorsmentioning

confidence: 99%

Partial data reuse for nested loop computations: design space exploration for FPGA implementations

Park

Diniz²

2008

International Journal of Electronics

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Automated compiler analyses and transformation techniques aim at improving design productivity of the mapping process of applications expressed in high-level programming languages to FPGAs. These transformations allow a compiler tool to reduce the number of design cycles and eliminate tedious and error-prone low-level transformations required in this mapping process, while still leading to good designs. Scalar replacement, also known as register promotion, is a very important data-oriented transformation that leads to designs that reduce the number of external memory accesses, and thus reduce execution time, at the expense of storage resource's. In this article we present a combination of loop transformation techniques, namely loop unrolling, loop splitting, and loop interchange with scalar replacement to enable partial data reuse on computations expressed by tightly nested loops pervasive in image processing algorithms. We describe a performance modelling in the presence of partial data reuse. Our experimental results reveal that our model accurately captures the non-trivial execution effects of pipelined implementations in the presence of partial data reuse due to the need to fill-up data buffers. The model thus allows a compiler to explore a large design space with high accuracy, ultimately allowing quickly it to find better designs than designs with limited manual search or brute-force approaches.

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“…We may also eliminate unnecessary memory reads and writes by employing scalar replacement [12,28], which makes the reuse of data explicit by substituting the same register for read/write references that access the same memory location. However, we do not apply the scalar replacement transformation in the experiments described in this paper.…”

Section: Code Transformationsmentioning

confidence: 99%

Evaluating heuristics in automatically mapping multi-loop applications to FPGAs

Ziegler

Hall

2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

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This paper presents a set of measurements that characterize the design space for automatically mapping high-level algorithms consisting of multiple loop nests, expressed in C, onto an FPGA. We extend a prior compiler algorithm that derived optimized FPGA implementations for individual loop nests. We focus on the area-time tradeoffs associated with sharing constrained chip area among multiple computations represented by an asynchronous pipeline. Intermediate results are communicated on chip; communication analysis generates this communication automatically. Other analyses and transformations, also associated with parallelizing compiler technology, are used to perform high-level optimization of the designs. We vary the amount of parallelism in individual loop nests with the goal of deriving an overall design that makes the most effective use of chip resources. We describe several heuristics for automatically searching the space and a set of metrics for evaluating and comparing designs. From results obtained through an automated process, we demonstrate that heuristics derived through sophisticated compiler analysis are the most effective at navigating this complex design space, particularly for more complex applications.

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Increasing the Applicability of Scalar Replacement

Cited by 21 publications

References 12 publications

Lowering STM Overhead with Static Analysis

Lowering STM Overhead with Static Analysis

Partial data reuse for nested loop computations: design space exploration for FPGA implementations

Evaluating heuristics in automatically mapping multi-loop applications to FPGAs

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