Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash Arrays

Poliakov, Pavel; Blomme, Pieter; Pret, Alessandro Vaglio; Corbalan, Miguel Miranda; Gronheid, Roel; Verkest, D.; Houdt, J. Van; Dehaene, Wim

doi:10.1109/led.2011.2176099

Cited by 8 publications

(2 citation statements)

References 10 publications

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“…Cell-related variability, or intrinsic variability, has been largely studied and increases with the technology scaling. It can be divided as the device to device variability, like the process-induced Gaussian cell topology variability [6] or the non-uniform doping [7], and as the within die variability, like RTN [8], [9], [10]. However, considering now the embedded memory cells not alone but integrated in an array and controlled by complex logic and high voltage circuits, a systematic cell variability, or extrinsic variability, exists as well.…”

Section: Introductionmentioning

confidence: 99%

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Kempf¹,

Marca²,

Baron³

et al. 2018

2018 IEEE International Reliability Physics Symposium (IRPS)

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The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs testchips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is based first on analog bitmap acquisition on 512kB testchip, followed by correction of spatial variabilities like peripheral circuit influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally such an analysis tool enhances the advantageous properties of test chip, its large memory cell statistics and its product-like organization, to give more reliable data and yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level. I. Criteria Test structure Single device Test chip Statistics availability Low bits density High bits density Cell envirronement Limited Product like Memory defectivity Memory only Peripheral effect, memory array organization/ intersite variation Test time Low Need burn-in, or early failure binning (EWS) Test flexibility High. Limited by its embedded test modes (BIST, reliability test, DMA…) and register values.

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Section: Introductionmentioning

confidence: 99%

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Kempf¹,

Marca²,

Baron³

et al. 2018

2018 IEEE International Reliability Physics Symposium (IRPS)

View full text Add to dashboard Cite

show abstract

“…This result lowered the reliability of the threshold voltage. Although some investigations of the decrease in the cell-tocell interference for planar NAND flash memory devices have been performed, [15][16][17][18] systematic studies concerning the electrical characteristics of vertical NAND flash memory devices using a modified array structure have yet not been conducted.…”

mentioning

confidence: 99%

Enhancement of the electrical characteristics for vertical NAND flash memory devices using a modified array structure

An¹,

Kim²

2017

Jpn. J. Appl. Phys.

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The electrical characteristics of vertical NAND flash memory devices with a modified structure were investigated by using a technology computer-aided design simulation tool in order to reduce the cell-to-cell interference. The threshold voltage shift of memory devices with a modified cell with a protruding distance of 3 nm was reduced by 88% compared to that of conventional cell. When the programming operation of the target cell with a modified array structure is performed, the cell-to-cell interference decreases due to the programmed charges of adjacent cells.

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NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

Bohara

Vishvakarma

2019

J Comput Electron

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Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash Arrays

Cited by 8 publications

References 10 publications

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Enhancement of the electrical characteristics for vertical NAND flash memory devices using a modified array structure

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

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