Inductance and capacitance analytic formulas forVLSI interconnects

Delorme, Nicolas; Belleville, Marc; Chilo, J.

doi:10.1049/el:19960689

Cited by 90 publications

(26 citation statements)

References 7 publications

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“…The circuit values are calculated from the following formula [9], where t is the thickness, w is the width, h is the height and l is the interconnect length, respectively. 1.44 4 describes the overall circuit simulation model for EMI prediction.…”

Section: Simulation and Measurement Setupmentioning

confidence: 99%

EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation

Shin¹,

Hwang²,

Kim³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and farfield measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

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Section: Simulation and Measurement Setupmentioning

confidence: 99%

EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation

Shin¹,

Hwang²,

Kim³

2014

JSTS:Journal of Semiconductor Technology and Science

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“…The equivalent circuit model of the PCB trace used for noise injection and noise monitoring. (14) where t is the thickness, w is the width , h is the height, and l is the interconnect length [18]. The equivalent circuit model of the lead frame is displayed in Fig.…”

Section: Modeling Of Packagementioning

confidence: 99%

Electromagnetic Susceptibility Analysis of I/O Buffers Using the Bulk Current Injection Method

Kwak¹,

Nah²,

Kim³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, we present a set of methodologies to model the electromagnetic susceptibility (EMS) testing of I/O buffers for mobile system memory based on the bulk current injection (BCI) method. An efficient equivalent circuit model is developed for the current injection probe, line impedance stabilization network (LISN), printed circuit board (PCB), and package. The simulation results show good correlation with the measurements and thus, the work presented here will enable electromagnetic susceptibility analysis at the integrated circuit (IC) design stage.

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“…Fifty distributed lumps of Gamma type are considered for the complete interconnect length under consideration. The capacitance and inductance values are obtained from the expressions reported in Delorme, Belleville, & Chilo (1996) and Lu, Banerjee, Celik, & Dutton (2001). The far end of interconnect lines are terminated by a capacitive load of 30 fF.…”

Section: Simulation Setup For Coupled Linesmentioning

confidence: 99%

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Sharma¹,

Kaushik

Sharma

2013

International Journal of Electronics

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This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/ topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

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Inductance and capacitance analytic formulas forVLSI interconnects

Cited by 90 publications

References 7 publications

EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation

EMI Prediction of Slew-Rate Controlled I/O Buffers by Full-Wave and Circuit Co-Simulation

Electromagnetic Susceptibility Analysis of I/O Buffers Using the Bulk Current Injection Method

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

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