Influence mechanism of solder aging and thermal network model optimization of multi-chip IGBT modules

A junction temperature model based on heat flow distribution in an IGBT module with solder layer voids

“…This can easily lead to irreversible plastic deformation of the solder layer, resulting in rapid growth and the fusion of voids [ 6 ]. Even if the chip solder layer voids are small, the thermal resistance between the chip and the chip solder layer will rise sharply [ 7 ]. The chip solder layer voids seriously aggravate the uneven temperature distribution of the IGBT chip and cause the junction temperature to rise significantly [ 8 ], which leads to rapid peeling of the solder layer and accelerates the aging of the IGBT module [ 9 ].…”

“…Fan et al [ 19 ] proposed a method to identify baseplate solder layer voids and assess void damage indirectly using case temperature. Cai et al [ 20 ] discussed the effect of solder layer voids on a thermal impedance matrix and modified the thermal impedance matrix. Du et al [ 21 ] established an improved Cauer thermal network model with consideration of solder layer voids by studying non-penetrating chip solder layer voids, but the model had a large error when used to calculate the junction temperature of IGBT modules with penetrating chip solder layer voids.…”