Influence of Gate and Channel Engineering on Multigate Tunnel FETs: A Review

Dutta, Ritam; Konar, Sukumar Chandra; Paitya, Nitai

doi:10.1007/978-981-13-8687-9_31

Cited by 15 publications

(4 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…All the simulations were performed in Silvaco Atlas device simulator. In this work, non-local band-to-band-tunneling (BTBT) model is used to consider the lateral direction tunneling movement of carriers [17][18][19].…”

Section: Resultsmentioning

confidence: 99%

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Dutta*,

Paitya,

Majumdar

2020

IJRTE

View full text Add to dashboard Cite

 Abstract: Continuous device scaling of tunnel field effect transistors (TFET) faces real challenges in low power VLSI applications. Here in this article, the major limitation of TFET i.e. Ambipolar conduction behavior has been thoroughly discussed and remedies to suppress the leakage current (I OFF ) has also been investigated. A thin pocket layers is incorporated in source and drain regions separately at Silicon on Insulator (SOI) TFET, keeping supply voltage (V DD ) at 0.5 V. The detail analytical modeling of surface potential distribution along the channel, electric field and tunneling current is derived in this paper. Using two-dimensional numerical device simulator, the various designs are modeled and validated with our proposed methodology. Non-local Band-to-Band tunneling (BTBT) is used for simulation purpose. It is observed that a drain pocket actually helps to reduce the ambipolar conduction and provide better drive current (I ON ) for fast switching. This further improves the I ON /I OFF ratio and also results better subthreshold swing (SS) as 27.43mV/decade to optimize the device characteristics.

show abstract

Section: Resultsmentioning

confidence: 99%

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Dutta*,

Paitya,

Majumdar

2020

IJRTE

View full text Add to dashboard Cite

show abstract

“…12,13 To overcome these two drawbacks, a number of alternative design techniques as well as non-planar structures have been proposed in the literature. Among these, band gap engineering, 14,15 gate oxide engineering, 16,17 source/drain material engineering, 18,19 multi gate technique [20][21][22] have been proposed to enhance the on current in the TFET. Gate-drain overlap structure 23,24 was suggested in the literature to suppress the ambipolar current.…”

Section: Introductionmentioning

confidence: 99%

Drain current model for a hetero‐dielectric single gate tunnel field effect transistor (HDSG TFET)

Singh

Fui

Soong

2021

Int J Numerical Modelling

View full text Add to dashboard Cite

Tunnel field effect transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower SS (subthreshold swing, <60 mV/ decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the analytical current model for Hetero-dielectric single gate (HDSG) TFET structure without using any iterative method. The developed analytical models show a good agreement with 2-D TCAD simulator results. The model is used to study the electrical behavior of the proposed device under various physical and bias variations.

show abstract

“…In spite of these advantages, TFET devices meet considerable challenges in producing better ON-state current (ION). To overcome this problem, several typical device structures with gate and material engineering have been studied [7][8][9][10][11][12][13][14]. Moreover, the supply voltage (VDD) needs to be lowered with device downsizing for low power applications.…”

Section: Introductionmentioning

confidence: 99%

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Dutta¹,

Paitya²

2021

J. Nano- Electron. Phys.

Self Cite

View full text Add to dashboard Cite

Influence of triple material having different work functions have been designed and investigated on a double gated P-i-N tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) for improved device performance. A III/V compound material (InAs) has been used in the source region for this n-channel heterojunction tunnel FET, because of which stress -strain effect results better tunneling. Graphene, being a low band gap material, has been used as nano ribbon to tune suitably the energy bandgap as less as possible. In this paper, the three different materials are introduced to restrict the drain -source reverse tunneling and also improve the TFET device performance in terms of surface potential distribution, lateral -vertical electric field variation and transfer characteristics. This triple material-based DG-PiN-TGNFET structure provides better subthreshold swing of 18.56 mV/decade at 0.5 V supply voltage compared to single and double material based double gated TGN-FET structures. The entire simulation has been performed using two-dimensional mathematical TCAD device software. Moreover, the low threshold voltage encourages the proposed device best suitable for low power logic applications.

show abstract

Influence of Gate and Channel Engineering on Multigate Tunnel FETs: A Review

Cited by 15 publications

References 16 publications

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Ambipolar Reduction Methodology for SOI Tunnel FETs in Low Power Applications: A Performance Report

Drain current model for a hetero‐dielectric single gate tunnel field effect transistor (HDSG TFET)

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Contact Info

Product

Resources

About