Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Jiang, Yuxi; Li, Jiao; Ran, Feng; Cao, Jialin; Dian-xiong, Yang

doi:10.1088/1674-4926/30/8/084007

Cited by 7 publications

(1 citation statement)

References 8 publications

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“…Therefore, the channel length L is usually designed to be 0.5μm-0.8μm in length. When designing W=nW UNIT with multi finger, the Fingered-Width W UNIT usually cannot exceed 50μm, and the number of fingers n uses even value [1], [4], [6]. Therefore, the key in design to solve the layout design of GGNMOS multi-fingered structure is DCGS, SCGS and BS, as shown in Figure 1 GGNMOS structural parameters [2,7].…”

Section: Esd Layout Optimization Design 31 Ggnmos Multi-finger Strucmentioning

confidence: 99%

Deep sub-micron ESD GGNMOS layout design and optimization

Shi

2018

MATEC Web Conf.

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In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Design Rule Check) command to check the distance between the N+ diffusion regions of different potentials so that ESD failure is prevented effectively. TLP (Transmission Line Pulse) current pulse signal is adopted to measure characteristics of the GGNMOS. The thesis descripts a ESD Optimal layout design from five aspects of introduction, Key elements of ESD circuits layout design, ESD layout optimization, a ESD GGNMOS layout instance and conclusion.

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Section: Esd Layout Optimization Design 31 Ggnmos Multi-finger Strucmentioning

confidence: 99%

Deep sub-micron ESD GGNMOS layout design and optimization

Shi

2018

MATEC Web Conf.

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TCAD Validation of the Model

Buccella

Stefanucci

Kayal

et al. 2018

Analog Circuits and Signal Processing

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Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

Wu¹,

Zong-guang²,

Genshen³

et al. 2020

J. Semicond.

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In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

show abstract

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Cited by 7 publications

References 8 publications

Deep sub-micron ESD GGNMOS layout design and optimization

Deep sub-micron ESD GGNMOS layout design and optimization

TCAD Validation of the Model

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

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