Influence of low thermal budget pre-anneals on the high temperature redistribution of low energy boron implants in silicon

Boucard, F.; Schott, Marco; Mathiot, D.; Rivallin, P.; Holliger, P.; Guichard, E.

doi:10.1557/proc-669-j8.3

Cited by 5 publications

(1 citation statement)

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“…FLA using a 20 ms pulse.-In general, optimized preheating is believed to influence strongly the initial self-interstitial distribution, thus causing an appreciable reduction in the TED 14 and limiting the undesirable junction broadening. It is commonly agreed that T p controls dopant diffusion while T max determines dopant activation.…”

Section: Resultsmentioning

confidence: 99%

Advanced Thermal Processing of Ultrashallow Implanted Junctions Using Flash Lamp Annealing

Skorupa

Gebel²,

Yankov³

et al. 2005

J. Electrochem. Soc.

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The use of flash lamp annealing for ultrashallow junction formation in silicon has been described. Low energy boron and arsenic implants have been heat-treated in this way using peak temperatures in the range of 1100 to 1300°C and effective anneal times of 20 and 3 ms. Secondary ion mass spectrometry and four-point probe measurements have been undertaken to determine the junction depth and the sheet resistance, respectively. Optimum processing conditions have been identified, under which one can obtain combinations of junction depth and sheet resistance values that meet the 90 nm technology node requirements and beyond.Source/drain junction depths need to be reduced in line with the continuing scaling down of deep submicrometer devices in silicon. Currently, the technique of choice for producing ultrashallow junctions ͑USJs͒ that meet the specifications of the sub-90 nm node relies on the use of ultralow energy boron ion implantation followed by extremely short time thermal annealing. 1-3 The key structural parameters of a USJ are the sheet resistance R s and junction depth X j . According to the International Technology Roadmap for Semiconductors (ITRS) 2003 4 the realization of the 90 nm node, whose year of production is 2004, calls for R s ഛ 663 ⍀/ᮀ and X j ഛ 20.4 nm. The respective values for the 65 nm node, which is scheduled for the year 2006 are R s ഛ 884 ⍀/ᮀ and X j ഛ 13.8 nm.Thermal annealing techniques such as rapid thermal processing ͑RTP͒ and, more recently, spike RTP 1-3,5,6 have been adequate to control the processing of mainstream devices. These annealing methods, however, will soon become unsuitable for the USJs required in the near future. The reason is that the effective anneal times 7 used are still relatively long, being in the order of 1 s or more. The fabrication of USJs necessitates both very high annealling temperatures for achieving high electrical activation, and extremely short times of heat-treatment to minimize the effect of dopant transient enhanced diffusion ͑TED͒ 8 responsible for the undesirable junction broadening. The attempts to meet these two competing requirements have led to great interest in the development of alternative ultrafast heat-treatment methods, of which laser thermal processing ͑LTP͒ 9 and flash-assisted RTP ͑fRTP™͒ 10,11 are presently among the most promising ones.The common feature of all ultrafast thermal annealing processes is the use of a small thermal budget involving a high peak temperature, T max , coupled with a very short effective time of the anneal cycle and very high ramp-up/cool-down rates. LTP has some inherent problems associated with dopant deactivation and process integration. In fRTP™, the device structure is exposed to a short duration pulse or flash ͑on the order of milliseconds͒ of intense light produced by an arc lamp.We have developed and tested successfully an alternative version of ultrarapid thermal processing based on the use of a xenon flash lamp system, hereafter referred to as the flash lamp annealing ͑FLA͒ technique. Results of a p...

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Section: Resultsmentioning

confidence: 99%