Influence of Strained Si<sub>1-y</sub>Ge<sub>y</sub> Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

Chleirigh, C.N.; Olubuyide, O.O.; Hoyt, Judy L.

doi:10.1149/1.2355890

Cited by 7 publications

(1 citation statement)

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“…[22][23][24] The fact that this is not found here indicates that the reverse current becomes dominated by other processing-induced defects and other mechanisms. For typical operation conditions, trap-assisted tunneling 6,25,26 and band-to-band tunneling 26,27 are dominant in the investigated source/drain ͑S/D͒ junctions. This is associated with the high electrical field near the junction due to the presence of the phosphorus halo doping, employed for controlling the short-channel effect in deep submicrometer CMOS transistors.…”

Section: Thick Relaxed Epitaxial Ge Layersmentioning

confidence: 99%

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

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Extended-defect aspects of state-of-the-art Ge-on-Si materials and devices are discussed with an emphasis on the impact of postgrowth thermal budget on the structural and electrical epilayer characteristics. The observations on the annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations ͑TDs͒. For the present processing conditions, the leakage current of Ge complementary metal oxide semiconductor compatible p + n junctions becomes independent of the TD density at about 10 7 cm −2 . © 2009 The Electrochemical Society. ͓DOI: 10.1149/1.3267514͔ All rights reserved. Defect engineering is a common practice in silicon-based integrated circuit and solar cell technology and has been extensively investigated during the past 2 decades, leading to its successful implementation in manufacturing lines. In addition, for sub-45 nm technologies, strain engineering is required to boost the device performance in agreement with the International Technology Roadmap for Semiconductors. In recent years, strong research efforts have also been focusing on the use of Ge-based channels for the sub-22 nm complementary metal oxide semiconductor ͑CMOS͒ node, 1 whereby epitaxial Ge-on-Si has a very strong potential. This also opens the door to achieve a full monolithic integration of Ge and III-V materials on a silicon substrate, leading to system-on-chip applications. The main challenge of the epitaxial deposition of Ge on Si is the 4% lattice mismatch and the difference in thermal expansion coefficient, which readily leads to the buildup of mechanical stress and, subsequently, its relaxation by the generation of misfit and threading dislocations ͑TDs͒.2,3 Therefore, the control of misfit and TDs during both substrate preparation and device processing is a must to arrive at a good-yielding, high performing technology. The aim of this paper is to summarize our recent developments in Geon-Si materials and devices and to address the remaining challenges. An extensive overview of the foregoing work can be found in Chap. 4 of Ref. 4.The focus in this work is on the defect formation and control during the fabrication of Ge virtual substrates on silicon by chemical vapor deposition. Hereby, several approaches can be followed 2-4 to optimize the threading dislocation density ͑TDD͒ either by the use of a relaxed SiGe-graded buffer layer or by the direct deposition of a thick Ge epitaxial layer on silicon. Three different cases are considered, whereby the impact of a postgrowth ͑PG͒ anneal on the TDD is highlighted, and the impact on the electrical device performance is mainly evaluated through the leakage current of p + n junctions fabricated in these layers. The procedures to separate the area from the perimeter leakage current have been outlined previously. 5,6 It is demonstrated that a PG anneal or thermal budget may have both beneficial and detrimental effects, depending on the application and type of layer. For a relaxed virtual Ge substrate, the PG anneali...

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