InGaAs/AlAs triple-barrier p–i–n junction diode for realizing superlattice-based FET for steep slope

Yukimachi, Atsushi; Miyamoto, Yasuyuki

doi:10.7567/jjap.55.118004

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Steep switching devices are currently being researched in an effort to prolong the scaling merit of LSI and achieve lower power consumption. [6][7][8][9][10][11] Among these steep switching devices, the tunnel FET is a promising alternative to CMOS and has been studied extensively both experimentally [12][13][14][15][16][17][18][19][20][21] and theoretically. [22][23][24][25][26][27][28] Despite aiming for steep switching, most studies on TFETs face the challenge of TFETs not being steep due to the lack of on-current or high off-current.…”

Section: Introductionmentioning

confidence: 99%

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Fukuda

Nogami

Kunisada

et al. 2020

Jpn. J. Appl. Phys.

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This study investigated the device optimization scheme of a double-gate hetero-junction tunnel FET, which was expected to improve circuit performance. A thinner channel with a stronger electric field increases the tunnel on-current. Conversely, a thin channel results in a larger quantum sub-band energy and an effective bandgap, which decreases the tunnel on-current. Such tradeoffs are clarified by considering the quantum effects in a device simulation. Furthermore, the gate capacitance behavior, identified via device simulation, was considered, and it demonstrates that the double-gate hetero-junction tunnel FET has a substantial capacitance merit compared to CMOS transistors. The early stages of our work used the intrinsic delay for device optimization, as defined in the international technology roadmap for semiconductors. However, based on the comparison with the speed evaluation results of the ring oscillator, the device optimization scheme was improved. This was achieved by adopting a new effective delay index, based on the effective on-currents and effective gate capacitances. Studies on the CMOS device design also applied the concept of effective on-current; however, the design method presented herein is novel in that it introduced the concept of effective gate capacitance.

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Section: Introductionmentioning

confidence: 99%

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Fukuda

Nogami

Kunisada

et al. 2020

Jpn. J. Appl. Phys.

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“…[1][2][3][4][5] To push the scaling limit of silicon CMOS technology that has supported the evolution of LSI, devices with steep switching have been studied recently. [6][7][8][9][10][11] Among them, tunnel field-effect transistors (TFETs) have been most extensively studied, both experimentally [12][13][14][15][16][17][18][19][20] and theoretically. [21][22][23][24][25][26][27] Most of those TFETs were designed for realizing larger on-currents, smaller off-currents, and steep subthreshold slopes.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of short-channel effects of tunnel field-effect transistors

Fukuda

Asai

Hattori

et al. 2018

Jpn. J. Appl. Phys.

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Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal–oxide–semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

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Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors

Beckers

Thewissen

Sorée

2018

Journal of Applied Physics

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This paper investigates energy filtering in silicon nanowires and nanosheets by resonant electron tunneling through a geometric superlattice. A geometric superlattice is any kind of periodic geometric feature along the transport direction of the nanowire or nanosheet. Multivalley quantum-transport simulations are used to demonstrate the manifestation of minibands and minibandgaps in the transmission spectra of such a superlattice. We find that the presence of different valleys in the conduction band of silicon favors a nanowire with a rectangular cross section for effective energy filtering. The obtained energy filter can consequently be used in the source extension of a field-effect transistor to prevent high-energy electrons from contributing to the leakage current. Self-consistent Schrödinger-Poisson simulations in the ballistic limit show minimum subthreshold swings of 6 mV/decade for geometric superlattices with indentations. The obtained theoretical performance metrics for the simulated devices are compared with conventional III-V superlatticeFETs and TunnelFETs. The adaptation of the quantum transmitting boundary method to the finite-element simulation of 3-D structures with anisotropic effective mass is presented in Appendixes A and B. Our results bare relevance in the search for steep-slope transistor alternatives which are compatible with the silicon industry and can overcome the power-consumption bottleneck inherent to standard CMOS technologies.

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InGaAs/AlAs triple-barrier p–i–n junction diode for realizing superlattice-based FET for steep slope

Cited by 3 publications

References 11 publications

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Circuit speed oriented device design scheme for GaAsSb/InGaAs double-gate hetero-junction tunnel FETs

Simulation study of short-channel effects of tunnel field-effect transistors

Energy filtering in silicon nanowires and nanosheets using a geometric superlattice and its use for steep-slope transistors

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