InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO<inf>2</inf> gate stack

20&#x2013;80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT&#x003D;1.2nm and lowest SS&#x003D;63mV/dec

“…However, the device metrics such as g m , V DD , SS, DIBL, and the L ch scaling of the III-V GAA devices demonstrated in [1] are still greatly limited by the large EOT of the devices. In this paper, we experimentally demonstrate InGaAs GAA nanowire MOSFETs with an EOT down to 1.2nm by the successful integration of ternary oxide dielectric LaAlO 3 (k~16) [3] . The reduction of EOT has allowed the demonstration of the first 20nm L ch InGaAs MOSFETs with g m as high as 1.74mS/μm at V ds =0.5V and negligible short channel effects (SCE).…”

Characterization and reliability of III-V gate-all-around MOSFETs

“…Reliability studies have been performed both on planar devices [18][19][20][21][22][23][24][25] and on nanowire MOSFETs [15,16]. The PBTI and HCI measurements are done with an automated measure-stress-measure (MSM) setup at various bias conditions and room temperature.…”

“…Reliability performance of InGaAs MOSFETs have not met the criteria for massive production and unique reliability challenges on emerging III-V nanowire devices are also needed to be addressed [15][16][17][18][19][20][21][22][23][24][25]. Heat dissipation could also be a potential challenge, especially for GAA structures where the channel is surrounded by oxides and ALD-deposited gate metal, neither of which have high thermal conductivity.…”

(Invited) High-K Dielectrics / High-Mobility Channel MOSFETs

“…However, the measured effective channel mobility of surface channel InGaAs MOSFETs is usually less than 2000cm 2 /Vs [1][2][3]. The advantage of buried channel device structure is that by adding a barrier layer, the channel can be kept away from the problematic interface and thus boost the channel mobility.…”