Most state-of-the-art high-performance technologies are relying on strain engineering, based on either a global approach using highmobility substrates or the implementation of local stressors. It has been reported that strain in the channel region has an impact on not only the carrier mobility and the drive current but also on key parameters such as gate oxide quality, hot carrier performance, negative bias temperature instabilities, low frequency noise, radiation hardness, etc. This paper reviews recent insights concerning the reliability and gate oxide quality of strained CMOS technologies. Impact of different strain engineering approaches will be illustrated and critically discussed.