InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current

Peng, Yue; Han, Genquan; Wang, Hongjuan; Zhang, Chunfu; Liu, Yan; Wang, Yibo; Zhao, Shenglei; Zhang, Jincheng

doi:10.1016/j.spmi.2016.03.004

Cited by 15 publications

(5 citation statements)

References 24 publications

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“…Although traditional TFET have advantages, they are rarely used in practical applications due to low on-current and large subthreshold swing, mainly due to the low probability of band-to-band tunneling using the traditional point tunneling approach and the severe impact of trap-assisted tunneling effects [9]. To overcome the limitations of traditional TFET, several novel TFET structures have been proposed, including highdrain doping [10], nanowire [11], multi-gate [12], and heterojunction structures [13][14][15][16]. We envision the integration of TFET into TFT applications.…”

Section: Introductionmentioning

confidence: 99%

Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*

Lin,

Chu

2023

Nanotechnology

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In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the ION, resulting in a lower subthreshold swing (S.Savg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional TFETs, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.Savg is improved to 21.5 mV/dec with an ION/IOFF ratio of 106 at VD=0.2V. This is the first time that a TFT with a subthreshold swing of less than 60 mV/Dec has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

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Section: Introductionmentioning

confidence: 99%

Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*

Lin,

Chu

2023

Nanotechnology

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“…The small electron effective mass and moderate bandgap of the channel material [22] are effective to enhance I ON in TFET, which makes In x Ga 1−x N (a kind of III-Nitride materials) has been a promising material and gained a lot of interest for low power applications. Many physical doping In x Ga 1−x N TFETs have been investigated [22][23][24], exhibiting superior device performances in comparison with the conventional Si-based counterparts. Actually, the nature of the strong spontaneous and piezoelectric polarization effect along the (0001) orientation of III-Nitrides heterojunctions could provide attractive solutions for the design of TFETs.…”

Section: Introductionmentioning

confidence: 99%

A high performance InGaN tunnel FET with InN interlayer and polarization-doped source and drain

Mao

Yang

et al. 2020

Semicond. Sci. Technol.

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An InGaN tunneling field-effect transistor (TFET) with a polarization-doped source and drain as well as an InN interlayer (PD-IL TFET) is proposed and investigated by Silvaco-Atlas simulations for the first time. This device features the graded In x Ga 1−x N source and drain where the 'In' fraction increases linearly in the source while it decreases linearly in the drain along the (0001) orientation. The unique design could realize the high PD carrier concentration in source and drain at the same time, benefiting from the nature of the polarization effect in III-Nitride materials. Thus, the random dopant fluctuations caused by conventional physical doping could be avoided effectively. Simulation results show that the PD-IL TFET with a 2 nm thick InN interlayer and 'In' fraction of 0.75 could achieve ON-state current (I ON ) of 74 µA µm −1 , I ON /I OFF ratio of 10 13 and average subthreshold swing of as low as 1 mV dec −1 . The effect of InN interlayer thickness and 'In' fraction of In x Ga 1−x N on the electrical characteristics of the PD-IL TFET are investigated and analyzed systematically. In addition, the circuit analysis and the feasible fabrication process issues of the proposed device are also presented and discussed. These results could break a new path to realize TFETs without physical doping in low power electronics applications.

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“…To reduce the ambipolar conduction of TFETs, a lot of methods were suggested. These methods include increasing the gate drain distance or using heterogeneous gate dielectrics [12], using asymmetric source-drain doping [13] and using large bandgap heterostructures on the drain side [14]. Although the previous methods could reduce ambipolar conduction, they can lead to: reduction in the ON state current, increase in the drain series resistance and added process complexity [15].…”

Section: Introductionmentioning

confidence: 99%

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Elnaggar

Shaker

Fedawy

2019

Semicond. Sci. Technol.

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In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TFET by using the combined two methods. The ON to OFF current ratio (I ON /I OFF ) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (g m ) and unit-gain cutoff frequency ( f T ) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (t phl ) and overshoot voltage (V p ) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TFET over Si-TFET that makes the proposed design more advantageous in the field of analog and digital applications.

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InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current

Cited by 15 publications

References 24 publications

Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*

Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*

A high performance InGaN tunnel FET with InN interlayer and polarization-doped source and drain

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

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InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current

Cited by 15 publications

References 24 publications

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application *

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application *

A high performance InGaN tunnel FET with InN interlayer and polarization-doped source and drain

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

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Product

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Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*

Bilateral sidewall engineering Si_1–xGe_x iTFET for low power display application^*