Innovative Circuit Board Level Routing Designs for BGA Packages

Titus, A.H.; Jaiswal, B. L.; Dishongh, Terry

doi:10.1109/tadvp.2004.831864

Cited by 26 publications

(8 citation statements)

References 10 publications

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“…For determining the number of I/O pads to be routed from top layer directly, the logical step is to divide the I/Os in such a way that outer pads of the array (pads near the periphery) are routed from top layer while the inner I/O pads are routed from the bottom layer through vias. Our approach is again based on the "balls shifted as needed" method [15]. The design is done assuming a via-in-pad (VIP) type of via configuration.…”

Section: Computer-aided Design For Two-layer Routing-square Grid mentioning

confidence: 99%

“…Since , by symmetry If which is the minimum distance allowed between a pad and a via, it is then possible to fit a via between the I/O balls of the maximum ball density hexagonal array [15]. Since is dependent on and , this expression gives an upper bound on the value of via diameter for given and angle .…”

Section: By Pythagoras' Theoremmentioning

confidence: 99%

“…In this paper, the "balls shifted as needed" approach (see [15] for the original work) has been extended to the more complicated two-layer and three-layer PCB cases. This has been done to address practical circuit board designs which tend to have multiple routing layers allowing higher wiring density.…”

mentioning

confidence: 99%

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A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology

Titus

Jaiswal

2006

IEEE Trans. Adv. Packag.

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The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computeraided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.Index Terms-Area array layout, ball grid array (BGA), bumppad, chip-package codesign, flip-chip, I/O pads, routable array, routing designs.

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Section: Computer-aided Design For Two-layer Routing-square Grid mentioning

confidence: 99%

Section: By Pythagoras' Theoremmentioning

confidence: 99%

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A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology

Titus

Jaiswal

2006

IEEE Trans. Adv. Packag.

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“…One of the critical technology issues is to satisfy the ever-increasing pin number in a fixed area. Recently, staggered pin arrays, which are formed by shifting specific columns of grid pin arrays, are utilized to satisfy this technology issue [2]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Escape routing for staggered-pin-array PCBs

Ho¹,

Lee²,

Chang³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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To accommodate the ever-growing pin number of complex PCB designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggeredpin-array escape routing problem. Experimental results show that our approach successfully completed the routing for all testcases efficiently and effectively.

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“…Similar works are the routing for ball grid array (BGA) packages and pin grid array (PGA) packages, including [5], [12], [13], [14], [16], [18] and [19]. The work [18] used the geometric and symmetric attributes of the pin positions in the BGA packages to assign pins of the BGA.…”

Section: Previous Workmentioning

confidence: 99%

A routing algorithm for flip-chip design

Fang

Lin

Yuh

et al.

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ApplicationSpecific Integrated Circuit (ASIC) designs. In this paper, we propose the first router for the flip-chip package. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads, and then create the global routing path for each net. The detailed routing consists of three stages, cross point assignment, net ordering determination, and track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.

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Innovative Circuit Board Level Routing Designs for BGA Packages

Cited by 26 publications

References 10 publications

A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology

A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology

Escape routing for staggered-pin-array PCBs

A routing algorithm for flip-chip design

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