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High performance turbo machinery demands high shaft speeds, increased rotor flexibility, tighter clearances in flow passages, advanced materials, and increased tolerance to imbalances. Operation at high speeds induces severe dynamic loading with large amplitude journal motions at the bearing supports. Squeeze film dampers are essential components of high-speed turbo machinery since they offer the unique advantages of dissipation of vibration energy and isolation of structural components, as well as the capability to improve the dynamic stability characteristics of inherently unstable rotor-bearing systems. A bearing test rig is developed using 350 KW motor with variable frequency drive and has the potential of maximum operating speed up to 20,000 rpm. A squeeze film damper is used between the bearings and housing to reduce the unbalance forces transmitted to the pedestal by introducing an additional damping and thereby reduces the amplitude of vibration to acceptable level. The test rig instrumentation is capable of detecting bearing critical speed of the test rotor, and has been used for parametric studies and to monitor the temperature profile, vibration levels and pressure distribution of SFD oil film. The first critical speed of the test rotor is measured. The vibration level of the rotor system is increased with the rise of axial load together with speed. It is estimated that under all the conditions presence of oil in SFD zone reduces the vibration levels.

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computeraided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.Index Terms-Area array layout, ball grid array (BGA), bumppad, chip-package codesign, flip-chip, I/O pads, routable array, routing designs.