Input ordering for low power in CMOS logic gates

Panwar, Ramesh; Rennels, D. A.

doi:10.1080/00207219508926221

International Journal of Electronics

1995

DOI: 10.1080/00207219508926221

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Input ordering for low power in CMOS logic gates

Ramesh Panwar

D. A. Rennels

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1997

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Power optimization for FPGA look-up tables

Alexander

1997

Proceedings of the 1997 International Symposium on Physical Design - ISPD '97

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We explore a new method for reducing power consumption/dissipation for FPGAs which is complementary to existing FPGA technology-mapping power-reduction techniques (e.g., [I@). Our approach is to reorder the input signals to the k-input look-up tables (k-LUTs) SO that switching activity (and hence power dissipation) inside the look-up tables is minimized. We present algoTithms which compute switching activity inside k-LUTs in optimal time. Our experimental results indicate that k-LUT input ordering is very effective at Teducing power dissipation within k-LUTs, providing savings of 26 % on average [2] (savings us. maximum are even greater).

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Power optimization for FPGA look-up tables

Alexander

1997

Proceedings of the 1997 International Symposium on Physical Design - ISPD '97

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Input ordering for low power in CMOS logic gates

Cited by 1 publication

References 7 publications

Power optimization for FPGA look-up tables

Power optimization for FPGA look-up tables

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