In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible for 20-25% of the power consumed in the Icache. Reducing the power consumed by the cache controller is important for low power I-cache design. We present three a r chitectural modications, which in concert, allow us to reduce the cache controller activity to less than 2% for most applications. The rst modication involves comparing cache tags for only those instructions that result in fetches from a new cache block. The second modication involves the tagging of those branches that cause instructions to be fetched f r om a new cache block. The third m o dication involves augmenting the I-cache with a small on-chip memory called the S-cache. The most frequently executed b asic blocks of code are statically allocated to the S-cache before p r ogram execution. We present empirical data to show the eect that these modications have on the cache controller activity.

No abstract

A PACS prototype has been installed and evaluated at the University of Washington. This paper presents the work done in the performance evaluation of the PACS prototype. The work involved network and workstation performance measurements and development of a simulation model based on the performance measurements. The simulation model was then used to do a parametric study of the PACS prototype to pinpoint the bottlenecks and suggest corrective measures. Results show that there are some local bottlenecks in the PACS prototype and an overall global bottleneck in the Data Management System (DM5) which forms the hub of the PACS prototype.

No abstract

No abstract