Input vulnerability‐aware approximate triple modular redundancy: higher fault coverage, improved search space, and reduced area overhead

Abstract

Area overhead reduction in conventional triple modular redundancy (TMR) by using approximate modules has been proposed in the literature. However, the vulnerability of approximate TMR (ATMR) in the case of a critical input, where faults can lead to errors at the output, is yet to be studied. Here, identifying critical input space through automatic test pattern generation and making it unavailable for the technique of approximating modules of TMR (ATMR) were focused, which involves a prime implicant reduction expansion. The results indicate that the proposed method provides 75-98% fault coverage, which amounts up to 43.8% improvement over that achieved previously. The input vulnerability-aware approach enables a drastic reduction in search space, ranging from 41.5 to 95.5%, for the selection of candidate ATMR modules and no compromise on the area overhead reduction is noticed.

Approximate Triple Modular Redundancy: A Survey

“…The criticality of input space was utilized by partial TMR for FPGA in [19]. References [12] and [9] introduced input vulnerability in ATMR [20], by utilizing automatic test pattern generation (ATPG) to recognize critical inputs and avoid approximation in that space. Reference [21] highlighted that approximations can compromise data accuracy and ATMR methods are restricted by theoretical and mathematical constraints for the assurance of fault masking.…”

“…Reference [11] necessitates the consideration of large variation of approximations and well-defined criteria for identifying optimal ATMR using a combination of approximate modules from list of approximate candidates. References [9], [12], and [20] set a clear criterion for the selection of the best combination by using the blocking property and the literal count. Blocking refers to those input vectors whose output can no longer be complemented and should necessarily hold the same value as the original function which ensures that at each input vector only one approximate module differs from the original circuit.…”

Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

“…It should be noted that the entire input space does not hold equal significance as some portion of the input space is more vulnerable to errors than the rest [16,17] (i.e., the portion of the input space which makes the maximum number of errors observable at the primary outputs). During the process of generating 32,000 random vectors for assigning detectability to each implication, some of the vectors could be selected from the portion of the input space, which is less vulnerable to errors.…”

“…Thus, instead of using 32,000 randoms vectors in the realization of prime implications, we explore the use of a specified input space [16] that is most vulnerable to errors. Input-aware vectors in compressed form can be obtained for each fault using an ATPG like ATALANTA [18] which is a publicly available ATPG tool based on the fan-out oriented (FAN) algorithm.…”

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

“…However, TMR suffers from a 200% area overhead problem [10,11]. Previous works on fault tolerance techniques have proposed the use of selective hardening methods such as Partial TMR [12], Selective TMR [13] and Approximate TMR (ATMR) [11,14,15] to overcome this area overhead issue of TMR without significantly compromising the fault masking. In the concept of selective hardening, the word 'Selective' implies that the protection method is providing full protection to selected part of the circuit/system.…”