Inside the FFT Black Box

Chu, Eleanor; George, Alan

doi:10.1201/9781420049961

Cited by 50 publications

(26 citation statements)

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“…Bit-reversing the output can be avoided if the input is already given in bit-reversed form or if butterflies and permutations are intertwined. In the notation of Chu and George [2] we therefore distinguish the following three kinds of DIF algorithms.…”

Section: Dif Algorithmsmentioning

confidence: 99%

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Lifting a Butterfly – A Component‐Based FFT

Schupp

2003

Scientific Programming

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Abstract. While modern software engineering, with good reason, tries to establish the idea of reusability and the principles of parameterization and loosely coupled components even for the design of performance-critical software, Fast Fourier Transforms (FFTs) tend to be monolithic and of a very low degree of parameterization. The data structures to hold the input and output data, the element type of these data, the algorithm for computing the so-called twiddle factors, the storage model for a given set of twiddle factors, all are unchangeably defined in the so-called butterfly, restricting its reuse almost entirely. This paper shows a way to a component-based FFT by designing a parameterized butterfly. Based on the technique of lifting, this parameterization includes algorithmic and implementation issues without violating the complexity guarantees of an FFT. The paper demonstrates the lifting process for the Gentleman-Sande butterfly, i.e., the butterfly that underlies the large class of decimation-in-frequency (DIF) FFTs, shows the resulting components and summarizes the implementation of a component-based, generic DIF library in C ++ .

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Section: Dif Algorithmsmentioning

confidence: 99%

“…Since our purpose merely is to keep the presentation selfcontained we refer the interested reader to the various textbooks and surveys, e.g. [2,4,8,16,34], for a more thorough discussion. Sections 3 and 4 form the two core sections of the paper.…”

Section: Introductionmentioning

confidence: 99%

Lifting a Butterfly – A Component‐Based FFT

Schupp

2003

Scientific Programming

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“…By doing these operations up to 4 cycles, the first buffer has a [0] , a [7] , a [10] , a [13] , the second buffer a [1] , a [4] , a [11] , a [14] , and so on. For the first radix-4 module, a [0] , a [4] , a [8] , a [12] are read from each data buffer in parallel without any delay.…”

Section: Fast Fourier Transformmentioning

confidence: 99%

“…At the second cycle, a [4] , a [5] , a [6] , a [7] are fed with one permutation so that the data are stored such as a [7] , a [4] , a [5] , a [6] . Note that a [4] is stored in the second buffer not the first one. By doing these operations up to 4 cycles, the first buffer has a [0] , a [7] , a [10] , a [13] , the second buffer a [1] , a [4] , a [11] , a [14] , and so on.…”

Section: Fast Fourier Transformmentioning

confidence: 99%

Energy-efficient signal processing using FPGAs

Choi¹,

Scrofano²,

Prasanna³

et al. 2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.

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“…For example, it takes 9 hours to obtain the results of physical quantities on a Pentium 1G PC if the object has 21240 unknowns [5,6]. To increase the computational speed, we need to parallelize [7,8] the existing pre-corrected-FFT algorithm for electrically large systems. In this algorithm, FFT occupies most of CPU time (up to about 75%).…”

Section: Introductionmentioning

confidence: 99%

MPI-Based Parallelized Precorrected FFT Algorithm for Analyzing Scattering by Arbitrarily Shaped Three-Dimensional Objects

Li¹,

Wang²,

Li³

2003

PIER

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Abstract-In this paper, how to parallelize the Pre-corrected FFT algorithm for solving the scattering problem of large scale is presented and discussed. The P-FFT technique developed by our group earlier was extended in the current analysis. To show the efficiency of the MPI-based parallelization algorithm, the experiment results are given in the latter part of the paper and various comparisons are made for such a demonstration.

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Inside the FFT Black Box

Cited by 50 publications

References 0 publications

Lifting a Butterfly – A Component‐Based FFT

Lifting a Butterfly – A Component‐Based FFT

Energy-efficient signal processing using FPGAs

MPI-Based Parallelized Precorrected FFT Algorithm for Analyzing Scattering by Arbitrarily Shaped Three-Dimensional Objects

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