Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

Fan, Jiewen; Li, Ming; Xu, Xiaoyan; Yang, Yuancheng; Xuan, Haoran; Huang, Ru

doi:10.1109/ted.2014.2371916

Cited by 126 publications

(30 citation statements)

References 16 publications

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“…Multiple-gate transistors such as FinFETs are believed to have smaller GIDL than planar MOSFETs due to the reduction of the electric field provided by the fully depleted body [10], [11]. Although nanowire and nanosheet transistors are usually expected to have negligible GIDL, the strong gate coupling generated by the reduced dimensions is responsible for the increase of the longitudinal band-to-band tunneling (L-BTBT) of electrons from the body to the drain [12], [13], additionally to the transverse BTBT.…”

Section: Introductionmentioning

confidence: 99%

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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Souza

Cerdeira

Estrada

et al. 2023

IEEE J. Electron Devices Soc.

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In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.

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Section: Introductionmentioning

confidence: 99%

“…The GIDL effect in nanowire transistors has been modeled and investigated through simulations and some experimental data, as in [12], [18], [19], at room temperature. To the best of the authors' knowledge, experimental measurements of GIDL at high temperatures were reported only at [9,20].…”

Section: Introductionmentioning

confidence: 99%

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

Souza

Cerdeira

Estrada

et al. 2023

IEEE J. Electron Devices Soc.

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“…A ground plane (GP) doping approach has been adopted as an effective approach for suppressing parasitic channel leakage current [5,8] for bulk Si substrate device. Higher the GP doping concentration in the scaled GAA NS-FET may results in other issues, such as bandto-band tunneling (BTBT) induced serious gate-induced drain leakage (GIDL) effect [9], carrier velocity degradations and performance variations [10]. Other approaches for suppressing parasitic-channel effect, such as bottom dielectric isolation approach [11] with additional complexity or silicon on insulator (SOI) substrates [12], have also been reported for better PEC control.…”

Section: Introductionmentioning

confidence: 99%

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

Zhang

et al. 2022

IEEE J. Electron Devices Soc.

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“…Therefore, new transistor architectures and new materials are desired to boost the IC performance with further scaling-down [19,20]. Semiconductor nanowires have demonstrated wide potential applications with respect to their unique properties [21][22][23][24] and possible compatibility with current processing technology, and therefore are likely to be building blocks for future nano-devices [25][26][27][28][29][30].…”

Section: Introductionmentioning

confidence: 99%