Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations

Ferlet-Cavrois, V.; Gasiot, Gilles; Marcandella, Claude; D'hose, C.; Flament, O.; Faynot, O.; Pontcharra, J. de; Raynaud, C.

doi:10.1109/tns.2002.805439

Cited by 87 publications

(25 citation statements)

References 21 publications

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“…This result demonstrates that even under a constantLET irradiation the widths of SET pulses fluctuatestrongly. This is reasonable because the position of the incident particle is entirely random during theHeavy Ion test, and the transient current response is affected seriously on the particleincident position in the device (such as a drain strike or a gate strike) (Cavrois and Gasiot, 2002).All of three kind devices have similar distribution of SET pulse width. Thismaybe due to similar device structure with roughly the same charge collection effects of single event in SOI device.…”

Section: Figure3mentioning

confidence: 91%

Comparison of Various Body Contact MOSFETs on Single Event Transients in 130 nm Partially Depleted SOI Process

2016

Rev. Téc. Ing. Univ. Zulia.

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Many papers show that floating-body devices have longer single-event transient(SET) than devices with bodycontact in SOI process. There are two main reasons for this phenomenon, one is because the Propagation Induced Pulse Broadening (PIPB) effect causes the pulsebroadening as the single-event transient propagates through the circuit which may affect the SET measuring results, and another is floating-body devices intrinsic lower vulnerability of SET. In previous papers, someone using TCAD simulation to prove that SOI device with and without body contact have identical SET sensitivity. However, they have no actual measurement result validating this similarity. In this work, we implement multiple identical short inverter chain in parallel to measure SET pulses avoiding PIPB effect, which demonstrates that the single-event transient vulnerability of SOI device with and without body-contact is similar and the main cause of SET pulse in floating-body devices becoming wider is the effect of PIPB. Results show that under a constant LET of 37.6 MeV-cm 2 /mg, singleevent transient pulse widths for 130nm PDSOI device ranges from 210 to 735 ps.

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Section: Figure3mentioning

confidence: 91%

Comparison of Various Body Contact MOSFETs on Single Event Transients in 130 nm Partially Depleted SOI Process

2016

Rev. Téc. Ing. Univ. Zulia.

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“…This mechanism is comparable to the bipolar transistor effect in partially depleted SOI transistors (Massengill et al, 1990). Because bipolar amplification is less important for fully depleted than for partially depleted devices, circuits based on fully depleted transistors are less sensitive to singleevent upset than partially depleted circuits (Ferlet-Cavrois et al, 2002). The effect of the parasitic bipolar transistor in SOI devices is quantified using the bipolar gain, .…”

Section: Bipolar Amplificationmentioning

confidence: 96%

“…This can be explained by the huge deposited charge by the ion which masks the impact of other phenomena such as the electrostatic control by the gate. Previous experimental and theoretical studies showed that, generally, fully depleted SOIbased devices (with either single-or double-gate configuration) present reduced floating body effects and then lower bipolar amplification of the collected charge than partiallydepleted SOI devices (Ferlet-Cavrois et al, 2002;Ferlet-Cavrois et al, 2005). In Multiple-Gate devices the control of the channel by the gates is naturally reinforced, and reduces even more the floating body effects.…”

Section: Bipolar Amplificationmentioning

confidence: 99%

3-D Quantum Numerical Simulation of Transient Response in Multiple-Gate Nanowire MOSFETs Submitted to Heavy Ion Irradiation

Munteanu¹,

Autran²

2011

Numerical Simulations - Applications, Examples and Theory

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“…The parasitic bipolar transistor still exists, but its gain is greatly reduced and less charge can be deposited in the thinner channel layer [78]. However, current amplification is still possible [79] and leads to significant single event effects.…”

Section: Single Event Effects In Soi Transistorsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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Insights on the transient response of fully and partially depleted SOI technologies under heavy-ion and dose-rate irradiations

Cited by 87 publications

References 21 publications

Comparison of Various Body Contact MOSFETs on Single Event Transients in 130 nm Partially Depleted SOI Process

Comparison of Various Body Contact MOSFETs on Single Event Transients in 130 nm Partially Depleted SOI Process

3-D Quantum Numerical Simulation of Transient Response in Multiple-Gate Nanowire MOSFETs Submitted to Heavy Ion Irradiation

Magnetic Random Access Memory for Embedded Computing

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