2011 International Symposium on Electronic System Design 2011
DOI: 10.1109/ised.2011.50
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Instruction Scheduling on Variable Latency Functional Units of VLIW Processors

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Cited by 6 publications
(3 citation statements)
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“…A short path activation function set of rules become proposed in [16] to enhance the accuracy of the hold logic and to optimize the performance of the variable-latency circuit. A training scheduling set of rules changed into proposed in [17] to schedule the operations on non-uniform latency practical devices and enhance the overall performance of Very long instruction word processors. In [18], variable latency pipelined multiplier architecture with a booth algorithm became proposed.…”
Section: Introductionmentioning
confidence: 99%
“…A short path activation function set of rules become proposed in [16] to enhance the accuracy of the hold logic and to optimize the performance of the variable-latency circuit. A training scheduling set of rules changed into proposed in [17] to schedule the operations on non-uniform latency practical devices and enhance the overall performance of Very long instruction word processors. In [18], variable latency pipelined multiplier architecture with a booth algorithm became proposed.…”
Section: Introductionmentioning
confidence: 99%
“…These research designs were able to decrease the timing waste of traditional circuits to improve performance, however they didn't consider the aging effect and couldn't adjust themselves during the runtime. A variable-latency adder design that considers the aging effect was proposed in [6] and [7]. Be that as it may, no variable-latency multiplier design that considers the aging effect and can adjust progressively has been finished.…”
Section: Introductionmentioning
confidence: 99%
“…For example, several variable-latency adders were proposed using the speculation technique with error detection and recovery [13]- [15]. A short path activation function algorithm was proposed in [16] to improve the accuracy of the hold logic and to optimize the performance of the variable-latency circuit. An instruction scheduling algorithm was proposed in [17] to schedule the operations on non-uniform latency functional units and improve the performance of Very Long Instruction Word processors.…”
Section: Introductionmentioning
confidence: 99%