Instruction Selection in ASIP Synthesis Using Functional Matching

Arora, Nidhi; Chandramohan, Kiran; Pothineni, Nagaraju; Kumar, Anshul

doi:10.1109/vlsi.design.2010.68

Cited by 10 publications

(6 citation statements)

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“…This technique can not hand bit-wise operations and the matching time is also exponential in the worst case. Similar methods are presented in [3] [7].…”

Section: Introductionmentioning

confidence: 94%

An Efficient Method for Custom Instruction Mapping Under the Safety Assurance of Code Generation

Luo¹,

Yuchun²,

Wu³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

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Abstract-In the work flow of embedded systems, processor design is the critical technology to directly affect the performance of whole system. In this process, instruction mapping is responsible for identifying the portions of target application program which match with custom instruction (CI) and implementing code generation for extension processor. However, traditional instruction mapping approaches would not consider the problem of mapping safety so that the mapping result is not reliable. In addition, as target applications get more complex, the drawback of large time cost makes embedded system less efficient. In this paper, we build safety check to ensure that the matched subgraphs can really be executed by hardware accelerator. And we propose an efficient matching method according the logic information of application program to reduce matching time and search space. For overlapping matched subgraphs, we also build up Maximal Weight Independent Set-based model to obtain better speedup of extension processor and the experiment results show the superiority of our method.

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“…This technique can not hand bit-wise operations and the matching time is also exponential in the worst case. Similar methods are presented in [3] [7].…”

Section: Introductionmentioning

confidence: 94%

An Efficient Method for Custom Instruction Mapping Under the Safety Assurance of Code Generation

Luo¹,

Yuchun²,

Wu³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

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“…This work is different from all above benchmarking and characterization work as it perform a comprehensive system-level (power, performance, ED X P) analysis of various big data applications and big data micro-benchmarks on two substantially different platforms one with high performance big core and another with low power little core to understand which of these two architectures is the choice for efficient big data processing. There has been also a number of research into application-specific [28,29] and domain-specific accelerators [30,31,32,33]. Using tightly integrated FPGA [27,34] with CPU, and GPU with CPU [1,22], to accelerate big data processing have been proposed in recent work.…”

Section: Related Workmentioning

confidence: 99%

Heterogeneous chip multiprocessor architectures for big data applications

Homayoun

2016

Proceedings of the ACM International Conference on Computing Frontiers

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Emerging big data analytics applications require a significant amount of server computational power. The costs of building and running a computing server to process big data and the capacity to which we can scale it are driven in large part by those computational resources. However, big data applications share many characteristics that are fundamentally different from traditional desktop, parallel, and scale-out applications. Big data analytics applications rely heavily on specific deep machine learning and data mining algorithms, and are running a complex and deep software stack with various components (e.g. Hadoop, Spark, MPI, Hbase, Impala, MySQL, Hive, Shark, Apache, and MangoDB) that are bound together with a runtime software system and interact significantly with I/O and OS, exhibiting high computational intensity, memory intensity, I/O intensity and control intensity. Current server designs, based on commodity homogeneous processors, will not be the most efficient in terms of performance/watt for this emerging class of applications. In other domains, heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. A heterogeneous architecture integrates cores with various micro-architectures and accelerators to provide more opportunity for efficient workload mapping. In this work, through methodical investigation of power and performance measurements, and comprehensive system level characterization, we demonstrate that a heterogeneous architecture combining high performance big and low power little cores is required for efficient big data analytics applications processing, and in particular in the presence of accelerators and near real-time performance constraints.

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“…Hence the patterns selected to cover one program graph may differ from those covering the other-and consequently may yield different code quality-even though both versions of the assembly code will produce the same value in the end. In an attempt to mitigate this issue Arora et al [28] introduced a method where the program graphs are first normalized before pattern matching, but the design is limited to arithmetic program DAGs and still does not guarantee that all matches will be found.…”

Section: Pattern Matching Is a Subgraph Isomorphism Problemmentioning

confidence: 99%