Instruction set extension for fast elliptic curve cryptography over binary finite fields GF(2/sup m/)

Groszschaedl, Johann; Kamendje, Guy-Armand

doi:10.1109/asap.2003.1212868

Cited by 31 publications

(18 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Research with respect to this has been undertaken in the context of F p [Gro02] and F 2 m [GK03] instruction-set extensions for general-purpose processors. Großschädl et al propose a Multiply ACumulate (MAC) architecture for a word-level instruction-set extension.…”

Section: Word Level Operations In F 2 163mentioning

confidence: 99%

ECC Is Ready for RFID – A Proof in Silicon

Hein¹,

Wolkerstorfer

Felber³

2009

Selected Areas in Cryptography

View full text Add to dashboard Cite

Abstract. This paper presents the silicon chip ECCon 1 , an Elliptic Curve Cryptography processor for application in Radio-Frequency Identification. The circuit is fabricated on a 180 nm CMOS technology. ECCon features small silicon size (15K GE) and has low power consumption (8.57 µW). It computes 163-bit ECC point-multiplications in 296k cycles and has an ISO 18000-3 RFID interface. ECCon's very low and nearly constant power consumption makes it the first ECC chip that can be powered passively. This major breakthrough is possible because of a radical change in hardware architecture. The ECCon datapath operates on 16-bit words, which is similar to ECC instruction-set extensions. A number of innovations on the algorithmic and on the architectural level substantially increased the efficiency of 163-bit ECC. ECCon is the first demonstration that the proof of origin via electronic signatures can be realized on RFID tags in 180 nm CMOS and below.

show abstract

Section: Word Level Operations In F 2 163mentioning

confidence: 99%

ECC Is Ready for RFID – A Proof in Silicon

Hein¹,

Wolkerstorfer

Felber³

2009

Selected Areas in Cryptography

View full text Add to dashboard Cite

show abstract

“…The range of possible ECC implementations is large: starting from pure software implementations, instruction-set extensions (ISE) became popular for 16-bit and 32-bit platforms to accelerate ECC over GF(2 m ) [3]. ISE are not useful for 8-bit platforms because slow data transport in 8-bit systems will deteriorate accelerated field operations.…”

Section: Related Workmentioning

confidence: 99%

A Low-Cost ECC Coprocessor for Smartcards

Aigner¹,

Bock

Hütter

et al. 2004

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. In this article we present a low-cost coprocessor for smartcards which supports all necessary mathematical operations for a fast calculation of the Elliptic Curve Digital Signature Algorithm (ECDSA) based on the finite field GF(2 m ). These ECDSA operations are GF(2 m ) addition, 4-bit digit-serial multiplication in GF(2 m ), inversion in GF(2 m ), and inversion in GF(p). An efficient implementation of the multiplicative inversion which breaks the 11:1 limit regarding multiplications makes it possible to use affine instead of projective coordinates for point operations on elliptic curves. A bitslice architecture allows an easy adaptation for different bit lengths. A small chip area is achieved by reusing the hardware registers for different operations.

show abstract

“…Finally, the boundary between hardware and software can also be defined at the level of custom instructions that are specifically designed to accelerate the field arithmetic, most notably the field multiplication [11]. Hardware/software co-design at the granularity of instruction set extensions provides the highest flexibility and requires the least amount of extra hardware of all approaches discussed in this section.…”

Section: Hardware/software Boundaries and Trade-offsmentioning

confidence: 99%

“…An alternative approach is to implement the field arithmetic in hardware and the curve/point arithmetic in software [1,2,7,14]. Furthermore, hardware acceleration at the granularity of instruction set extensions for the finite field multiplication has also been investigated [6,11,17]. Besides the hardware/software boundary, the interface between hardware accelerator and host processor is essential for the system performance, especially for "lowcost" accelerators without local storage since they require a high number of data transfers.…”

Section: Introductionmentioning

confidence: 99%

Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller

Koschuch

Lechner

Weitzer

et al. 2006

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. 8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrollers is often too poor for the implementation of public-key cryptography in software. In this paper we present a minimalist hardware accelerator for enabling elliptic curve cryptography (ECC) on an 8051 microcontroller. We demonstrate the importance of removing system-level performance bottlenecks caused by the transfer of operands between hardware accelerator and external RAM. The integration of a small direct memory access (DMA) unit proves vital to exploit the full potential of the hardware accelerator. Our design allows to perform a scalar multiplication over the binary extension field GF(2 191 ) in 118 msec at a clock frequency of 12 MHz. Considering performance and hardware cost, our system compares favorably with previous work on similar 8-bit platforms.

show abstract

Instruction set extension for fast elliptic curve cryptography over binary finite fields GF(2/sup m/)

Cited by 31 publications

References 23 publications

ECC Is Ready for RFID – A Proof in Silicon

ECC Is Ready for RFID – A Proof in Silicon

A Low-Cost ECC Coprocessor for Smartcards

Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller

Contact Info

Product

Resources

About