Instruction set extension for high throughput disparity estimation in stereo image processing

Banz, Christian; Dolar, Carsten; Cholewa, Fabian; Blume, Holger

doi:10.1109/asap.2011.6043265

Cited by 12 publications

(4 citation statements)

References 14 publications

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“…Typically, soft CPU customization is undertaken with the target of accelerating the most frequently used functions. This has resulted in performance improvements as reported in previous publications [5,6]. ISEs usually target applications where the CPU time is dominated by smaller code sections (i.e.…”

Section: Introductionmentioning

confidence: 61%

Generation of multi-core systems from multithreaded software

Wold

Tørresen

Agne

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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A heterogeneous system with soft CPU tailored to the individual threads of the application, while still software based, offers the potential for improved performance and resource utilization over a homogeneous system. In this paper we present a method to automatically create a heterogeneous multi-core system from a multithreaded software application. The resulting system consists of processing elements based on customized MIPS soft CPUs coupled with their respective programs. Using instruction set architecture (ISA) subsetting, we adapt the individual soft CPUs to the specific computations they have to perform. We have carried out a case study with a constraint solver application for which we find a performance increase of 1.54 accompanied with an area reduction of 22.5% compared to a homogeneous multicore system. We also present an automated toolchain that generates synthesizable IP-cores from software threads with little additional development overhead.

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Section: Introductionmentioning

confidence: 61%

Generation of multi-core systems from multithreaded software

Wold

Tørresen

Agne

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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show abstract

“…The number of index bits depends on the value set in the configuration register. In one cycle, the LFSR state is updated by the same number of LFSR steps as index bits used (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16). Additionally, the instruction set extension (ISE) is realized as a multi-cycle instruction, which allows handling of one sample in a number of cycles equal to the configured number of non-zero entries (I) per matrix column.…”

Section: Configurabilitymentioning

confidence: 99%

“…Application-specific instruction-set processors (ASIPs) can compensate for the performance degradation issue, since they are optimized for a specific application domain, providing increased efficiency and performance for the core algorithms of the domain's target applications. For instance, an ASIP optimized for stereo image processing can achieve up to 130× speed-up compared to a conventional processor [11]. These performance optimizations also lead to energy saving as in [12], where a processing core with few accelerators dedicated to biomedical applications, can achieve up to 11.5× energy saving compared the processing core-only implementation.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing

Constantin

Doğan

Andersson

et al. 2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog-and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime. The design is equipped with specific sub-VT capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.

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“…For instance, an ASIP optimized for stereo image processing can achieve up to 130x speed-up compared to a conventional processor [10]. These performance optimizations also lead to energy saving as in [11], where a processing core with few accelerators dedicated to biomedical applications, can achieve up to 11.5x energy saving compared the processing core-only implementation.…”

Section: Introductionmentioning

confidence: 99%

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Constantin

Doğan

Andersson

et al. 2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Abstract-Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.

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Instruction set extension for high throughput disparity estimation in stereo image processing

Cited by 12 publications

References 14 publications

Generation of multi-core systems from multithreaded software

Generation of multi-core systems from multithreaded software

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

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