Insulated gate field effect transistor integrated circuits with silicon gates

Faggin, Federico; Klein, Thomas; Vadasz, L.

doi:10.1109/t-ed.1969.16611

Cited by 9 publications

(2 citation statements)

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“…16 This is referred to as a buried contact, and it was originally developed to increase the interconnect density in early Metal-Oxide-Semiconductor (MOS) integrated circuits. 17,18 The advantages of the buried contact in the CCD context are a reduction in the area of the floating diffusion and the space needed for the connection from the floating diffusion to the output transistor, with resultant reductions in the total capacitance at the floating-diffusion node. Fig.…”

Section: Buried Contact Development and Noise Resultsmentioning

confidence: 99%

Technology and device-design enhancements for improved read noise performance in fully depleted CCDs

et al. 2014

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In this work we describe efforts to reduce the read noise in fully depleted, scientific charge-coupled devices (CCDs). The read noise is proportional to the total capacitance at the floating-diffusion node. Reductions in the capacitance at the floating diffusion are accomplished by implementing a direct contact between the output transistor, polysilicon-gate electrode and the floating diffusion. We have previously reported promising results for this technology that were measured on small-format CCDs with 4-channel readout where each channel had a different output transistor geometry. In this work we present the results of the use of this technology on 12 and 16-channel, large-format CCDs in order to determine the reproducibility of the process. The contact size for this work is two microns by two microns, and projection lithography was used to print the contacts. We have also utilized selective wafer-stepper lithography to generate contacts that are one micron on a side. We also describe efforts in the device design of the output transistor to further reduce the noise.

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Section: Buried Contact Development and Noise Resultsmentioning

confidence: 99%

Technology and device-design enhancements for improved read noise performance in fully depleted CCDs

et al. 2014

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“…-Doped polysilicon for self-aligned source/drain region which is also used as a hard mask for dopant diffusion and activation [5].…”

Section: Introductionmentioning

confidence: 99%

Total ionizing dose effects in multiple-gate field-effect transistor

Gaillardin

Marcandella

Martinez

et al. 2017

Semicond. Sci. Technol.

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This paper focuses on total ionizing dose (TID) effects induced in multiple-gate field-effect transistors. The impact of device architecture, geometry and scaling on the TID response of multiple-gate transistors is reviewed in both bulk and silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technologies. These innovating devices exhibit specific ionizing dose responses which strongly depend on their three-dimensional nature. Their TID responses may look like the one usually observed in planar two-dimensional bulk or SOI transistors, but multiple-gate devices can also behave like any other CMOS device.

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