International audienceIn this paper we investigate the Total Ionizing Dose (TID) response of an UltraThin Buried-OXide (UTBOX) on a Fully Depleted Silicon-On-Insulator (FDSOI) high-k/metal gate technology. The impact of thinning the BOX and of the use of a Ground Plane (GP) at the back side of the BOX on the TID behavior are discussed by comparing their results to ionizing radiation experiments performed on reference FDSOI devices

The impact of ion energy on single-event upset was investigated by irradiating CMOS SRAMs with low and highenergy heavy ions. A variety of CMOS SRAM technologies was studied, with gate lengths ranging from 1 to 0.5 pm and integration densities from 16 Kbit to 1 Mbit. No significant differences were observed between the low and high-energy single-event upset response. The results are consistent with simulations of heavy-ion track structures that show the central core of the track strucitures are nearly identical for low and high-energy ions. Three-dimensional simulations confirm that charge collection is similar in the two cases. Standard lowenergy heavy ion tests are more cost-effective and appear to be sufficient for CMOS technologies down to 0.5 pm. We discuss implications for deep submicron scaling, multiple-bit upsets, and hardness assurance.

Articles you may be interested inEffects of type of reactor, crystallinity of SiC, and N F 3 gas pressure on etching rate and smoothness of SiC surface using N F 3 gas plasma A process for achieving high yield of SiC through wafer via holes without trenching or micromasking and with excellent electrical connection after subsequent metal plating across full wafers was developed for use in high electron mobility transistors ͑HEMTs͒ and microwave monolithic integrated circuits ͑MMICs͒ using an inductively coupled plasma etch. Consideration was given to the choice of wafer platen, hard mask, gas chemistry, surface treatments, and plasma parameters in order to achieve an acceptable etch rate while at the same time minimizing trenching and micromasking that can harm via yield. In addition, the issue of wafer thickness variation and etch nonuniformity leading to punch through of Au pads at the bottom of the vias was addressed by the addition of a metal layer to the front side of the wafer. The etch rate achieved for 25% of a 2 in. diameter wafer is approximately 3800 Å / min while demonstrating acceptable levels of trenching and micromasking with little or no Au punch through. The final process has been demonstrated to achieve Ͼ95% yield across a full 2 in. diameter, 100 m thick wafer with a high density of vias.

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