Integer Computation of Lossy JPEG2000 Compression

Zhou

et al. 2018

Sensors

Conventional rational polynomial coefficients (RPC)-based orthorectification methods are unable to satisfy the demands of timely responses to terrorist attacks and disaster rescue. To accelerate the orthorectification processing speed, we propose an on-board orthorectification method, i.e., a field-programmable gate array (FPGA)-based fixed-point (FP)-RPC orthorectification method. The proposed RPC algorithm is first modified using fixed-point arithmetic. Then, the FP-RPC algorithm is implemented using an FPGA chip. The proposed method is divided into three main modules: a reading parameters module, a coordinate transformation module, and an interpolation module. Two datasets are applied to validate the processing speed and accuracy that are achievable. Compared to the RPC method implemented using Matlab on a personal computer, the throughputs from the proposed method and the Matlab-based RPC method are 675.67 Mpixels/s and 61,070.24 pixels/s, respectively. This means that the proposed method is approximately 11,000 times faster than the Matlab-based RPC method to process the same satellite images. Moreover, the root-mean-square errors (RMSEs) of the row coordinate (ΔI), column coordinate (ΔJ), and the distance ΔS are 0.35 pixels, 0.30 pixels, and 0.46 pixels, respectively, for the first study area; and, for the second study area, they are 0.27 pixels, 0.36 pixels, and 0.44 pixels, respectively, which satisfies the correction accuracy requirements in practice.

Section: Rpc-based Orthorectification Using An Fpga Chipmentioning

confidence: 99%

RPC-Based Orthorectification for Satellite Images Using FPGA

Zhou

et al. 2018

Sensors

“…Then, the coefficients are grouped into codeblocks, which are processed together using JPEG2000's entropy encoder, the embedded block coding with optimal truncation (EBCOT) process. 9 Encoding consists of a three stage process, beginning with the lossless compression of each codeblock in tier-I coding. Optimal truncation then performs rate-distortion optimization on the coefficients.…”

Section: Jpeg2000mentioning

confidence: 99%

Predicting exploitation success on compressed imagery through common image quality metrics: an initial look

2015

Imagery from unmanned aerial systems (UAS) needs compression prior to transmission to a receiver for further processing. Once received, automated image exploitation algorithms, such as frame-to-frame registration, target tracking, and target identification, are performed to extract actionable information from the data. Unfortunately, in a compress-then-analyze system, exploitation algorithms must contend with artifacts introduced by lossy compression and transmission. Identifying metrics that enable compression engines to predict exploitation degradation could allow encoders the ability of tailoring compression for specific exploitation algorithms. This study investigates the impact of H.264 and JPEG2000 compression on target tracking through the use of a multi-hypothesis blob tracker. Used quality metrics include PSNR, VIF, and IW-SSIM.

International Journal of Reconfigurable Computing

“…Discrete Wavelet Transform/Quantization. The proposed system implementation uses a lossy CDF 9/7 wavelet transform [11]. The lossy wavelet transform is chosen as it offers additional compression gain over the lossless implementation while still maintaining comparable image quality at lower compression ratios.…”

Section: Jpeg2000 Hardware Modulesmentioning

confidence: 99%

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

McNichols

Balster

Turri

et al. 2013

Self Cite

This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.