Integrated antennas on Si with over 100 GHz performance, fabricated using an optimized proton implantation process

Chan, Kai‐Chieh; Chin, Albert; Lin, Yu-De; Chang, Ching-Yun; Zhu, Chunxiang; Li, M.F.; Kwong, Dim‐Lee; McAlister, S.P.; Duh, D.S.; Lin, Wuu-Jyh

doi:10.1109/lmwc.2003.817146

Cited by 71 publications

(28 citation statements)

References 9 publications

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“…Others like in [4] propose to increase the gain by covering the whole chip with a lens which needs extra bulky space out of the chip. Meanwhile, the micromachining technique and proton implantation process have been proposed to improve the radiation efficiency by reducing the substrate losses [5][6], but the shielding problem from other circuitry would still remain. including bowtie antenna (from [7]).…”

Section: Introductionmentioning

confidence: 99%

Novel high efficiency CMOS on-chip antenna structures at millimeter waves

Pan

Wang

Capolino

2011

2011 IEEE International Symposium on Antennas and Propagation (APSURSI)

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Abstract-In this work, four designs of (Bi)CMOS on-chip antenna (OCA) at 90GHz and 140GHz are shown and compared, aiming at the difficult task of broadside radiation (off the top chip metal surface). A bowtie-shaped slot antenna is fabricated and expected to offer a gain of -1.5dB at 90GHz and 30GHz impedance bandwidth. Another design of slot antenna backed by a cavity, which is fully isolated from the circuits, gives a gain of -2 dB at 140GHz and 5 GHz bandwidth. Additionally, a design of a slot antenna based on an integrated waveguide in (Bi)CMOS showing -1 dB gain is proposed. At last, a proposed E-shaped patch antenna, which only occupies 0.7 mm× 0.7 mm area, shows -2 dB gain with 10 GHz bandwidth.

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Section: Introductionmentioning

confidence: 99%

Novel high efficiency CMOS on-chip antenna structures at millimeter waves

Pan

Wang

Capolino

2011

2011 IEEE International Symposium on Antennas and Propagation (APSURSI)

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“…Though the initial onchip antenna design has been reported almost a decade ago, not until recently, this concept has gained popularity in RF researchers. Many monolithic Si integrated antennas have been demonstrated in recent years [3][4][5][6]. The on-chip antenna design in literature is mostly restricted to higher frequencies like 10 GHz and above due to large size of antennas at lower frequencies.…”

Section: Introductionmentioning

confidence: 99%

“…The on-chip antenna design in literature is mostly restricted to higher frequencies like 10 GHz and above due to large size of antennas at lower frequencies. On-chip antennas, as described in the literature, are either utilized to provide inter and intra-chip wireless interconnects [3] or for short-range air transmission [4]. The former antennas display high transmission loss and are not characterized for element gain and radiation pattern whereas the latter often utilize additional processing steps to increase the resistivity of Si substrates in an attempt to enhance the antenna performance.…”

Section: Introductionmentioning

confidence: 99%

On-chip antenna: Practical design and characterization considerations

Shamim

Salama

Soliman

et al. 2010

2010 14th International Symposium on Antenna Technology and Applied Electromagnetics &Amp; The American Electromagnetics Confer

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Abstract-This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

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“…In [17], a special silicon lens is added at the bottom of the chip to improve the gain to 2 dBi. In [18], a costly ion implantation process is added to increase the substrate resistivity and improve the gain to 6.4 dBi. Besides the efficiency and cost issues, the on-chip antennas occupy a significant portion of IC area and provide poor horizontal radiation pattern, which limit their applications in inter-chip communications.…”

Section: Introductionmentioning

confidence: 99%

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

Chen

Joo

Sayilir

et al. 2009

IEEE J. Solid-State Circuits

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Abstract-A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10 8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.Index Terms-Bond-wire antenna, high-speed link, on-chip antenna, wirebond antenna, wireless inter-chip link, wireless transceiver.

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Integrated antennas on Si with over 100 GHz performance, fabricated using an optimized proton implantation process

Cited by 71 publications

References 9 publications

Novel high efficiency CMOS on-chip antenna structures at millimeter waves

Novel high efficiency CMOS on-chip antenna structures at millimeter waves

On-chip antenna: Practical design and characterization considerations

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

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