Integrated approach to improving local CD uniformity in EUV patterning

Liang, Andrew; Hermans, Jan; Tran, Timothy H.; Viatkina, Katja; Liang, C. R.; Ward, B. L.; Chuang, Steven S. C.; Yu, Jengyi; Harm, Greg; Vandereyken, Jelle; Río, David; Kubis, Michael; Tan, Samantha; Wise, Rich; Dusa, Mircea V.; Reddy, Sirish; Singhal, Akhil; Schravendijk, B. van; Dixit, G.; Shamma, Nader

doi:10.1117/12.2258192

Cited by 8 publications

(3 citation statements)

References 5 publications

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“…Lately at the 2016 SPIE Advanced Lithography conference, a good amount of papers was presented demonstrating the substantial research on Photosensitized CARs [27][28][29][30][31]. Moreover, some approaches have been introduced to improve sensitivity, LWR and local CDU from many directions [32,33].…”

Section: Status and Challengesmentioning

confidence: 99%

Promising Lithography Techniques for Next-Generation Logic Devices

2018

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Continuous rapid shrinking of feature size made the authorities to seek alternative patterning methods as the conventional photolithography comes with its intrinsic resolution limit. In this regard, some promising techniques have been proposed as next-generation lithography (NGL) that has the potentials to achieve both high-volume production and very high resolution. This article reviews the promising NGL techniques and introduces the challenges and a perspective on future directions of the NGL techniques. Extreme ultraviolet lithography (EUVL) is considered as the main candidate for sub-10-nm manufacturing, and it could potentially meet the current requirements of the industry. Remarkable progress in EUVL has been made and the tools will be available for commercial operation soon. Maskless lithography techniques are used for patterning in R&D, mask/mold fabrication and low-volume chip design. Directed self-assembly has already been realized in laboratory and further effort will be needed to make it as NGL solution. Nanoimprint lithography has emerged attractively due to its simple process steps, high throughput, high resolution and low cost and become one of the commercial platforms for nanofabrication. However, a number of challenging issues are waiting ahead, and further technological progresses are required to make the techniques significant and reliable to meet the current demand. Finally, a comparative study is presented among these techniques.

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Section: Status and Challengesmentioning

confidence: 99%

Promising Lithography Techniques for Next-Generation Logic Devices

2018

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“…Much work is already published on how to reduce local variations with co-optimization of patterning processes 9 . This is not discussed in this paper.…”

Section: Address Local Variationmentioning

confidence: 99%

Tough road ahead for device overlay and edge placement error

Bhattacharyya

2019

Metrology, Inspection, and Process Control for Microlithography XXXIII

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During the last several years we have seen an impressive drive in the industry to continue to innovate in order to keep up with the challenging requirements of overlay in multi-patterning processes. A major part of these efforts is spent in opening up of the flexibility in control knobs on process tools (mostly lithography and etch) enabling the high order actuation capability. In order to feed this high order actuation, it has also become important to address the need of input data accuracy, driving up the demand for improved metrology accuracy and sampling. Adding to the complexity, it has also become important to address edge placement error (EPE). EPE is basically the pattern fidelity of a device structure created by a multi-patterning process, defined as the relative displacement of the edges of two features from their intended target position. Here local CD error is an important parameter in addition to overlay. EPE requirements of a "single digit nanometer number" is now a harsh reality in 5nm nodes and below. In this technical presentation we will review the above developments and remaining gaps in technology (litho and dimensional metrology applications), as well as design and integration. Mitigation of such challenges need a large team effort that is industry-wide and not just limited to litho.

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“…Further improving LCDU by post processing after lithography can be very beneficial. Figure 7 shows that etching can improve the LCDU up to 40% in CAR resists 20 . Figure 7.…”

Section: Contrast Improvementmentioning

confidence: 99%

Improvements in resist performance towards EUV HVM

et al. 2017

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Extreme ultraviolet (EUV) lithography with 13.5 nm wavelength is the main option for sub-10nm patterning in the semiconductor industry. We report improvements in resist performance towards EUV high volume manufacturing. A local CD uniformity (LCDU) model is introduced and validated with experimental contact hole (CH) data. Resist performance is analyzed in terms of ultimate printing resolution (R), line width roughness (LWR), sensitivity (S), exposure latitude (EL) and depth of focus (DOF). Resist performance of dense lines at 13 nm half-pitch and beyond is shown by chemical amplified resist (CAR) and non-CAR (Inpria YA Series) on NXE scanner. Resolution down to 10nm half pitch (hp) is shown by Inpria YA Series resist exposed on interference lithography at the Paul Sherrer Institute. Contact holes contrast and consequent LCDU improvement is achieved on a NXE:3400 scanner by decreasing the pupil fill ratio. State-of-the-art imaging meets 5nm node requirements for CHs. A dynamic gas lock (DGL) membrane is introduced between projection optics box (POB) and wafer stage. The DGL membrane will suppress the negative impact of resist outgassing on the projection optics by 100%, enabling a wider range of resist materials to be used. The validated LCDU model indicates that the imaging requirements of the 3nm node can be met with single exposure using a high-NA EUV scanner. The current status, trends, and potential roadblocks for EUV resists are discussed. Our results mark the progress and the improvement points in EUV resist materials to support EUV ecosystem.

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Integrated approach to improving local CD uniformity in EUV patterning

Cited by 8 publications

References 5 publications

Promising Lithography Techniques for Next-Generation Logic Devices

Promising Lithography Techniques for Next-Generation Logic Devices

Tough road ahead for device overlay and edge placement error

Improvements in resist performance towards EUV HVM

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