Integrated-Circuit Logarithmic Arithmetic Units

Lang, T. J.; Żukowski, Mirosław; Lamaire,; Han, Chae

doi:10.1109/tc.1985.1676588

Cited by 24 publications

(6 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here partial sums are symbolically represented in the nodes of the graph while the edges are used to represent the shift amounts [28] Furthermore, different number representations have been used to take advantage of the inherent simplification of multiplication in them, like residue number system (RNS) [80][81][82][83][84] and LNS [85][86][87][88][89][90][91][92]. Most efforts towards utilizing LNS for digital filters have focused on either implementing the non-linear conversion to and from LNS, selecting the logarithm basis, or implementing the LNS addition and subtraction efficiently [92][93][94][95][96][97]. The finite word length filter design has not been considered, but instead relied on rounding the obtained coefficients to the nearest LNS number.…”

Section: Reduction In Multiplier Complexitymentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

View full text Add to dashboard Cite

Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

show abstract

Section: Reduction In Multiplier Complexitymentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

View full text Add to dashboard Cite

show abstract

“…Implementation work began with Swartzlander and Alexopoulos's 1975 paper [3], with a 12-bit device [4], while a 1988 scheme extended the width to 20 bits [5]. Both designs were direct implementations of Eqn.…”

Section: Addition and Subtractionmentioning

confidence: 99%

“…LNS addition and subtraction require lookup tables whose size grows exponentially (several times 2 l words), with logarithms that are of width l bits. For this reason, implementations described in the early literature were limited to 8-12 bits of fractional precision [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Logarithmic arithmetic as an alternative to floating-point: A review

Chugh

Parhami

2013

2013 Asilomar Conference on Signals, Systems and Computers

View full text Add to dashboard Cite

show abstract

“…Most efforts towards utilizing LNS for digital have focused on either implementing the nonlinear conversion to and from LNS, selecting the logarithm basis, or implementing the LNS addition and subtraction efficiently [12,23,[27][28][29][30]. The finite word length filter design has to the best of the authors' knowledge not been considered but instead relied on rounding the obtained coefficients to the nearest LNS number.…”

Section: Introductionmentioning

confidence: 99%

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Alam

Gustafsson

2014

VLSI Design

View full text Add to dashboard Cite

Logarithmic number system (LNS) is an attractive alternative to realize finite-length impulse response filters because of multiplication in the linear domain being only addition in the logarithmic domain. In the literature, linear coefficients are directly replaced by the logarithmic equivalent. In this paper, an approach to directly optimize the finite word length coefficients in the LNS domain is proposed. This branch and bound algorithm is implemented based on LNS integers and several different branching strategies are proposed and evaluated. Optimal coefficients in the minimax sense are obtained and compared with the traditional finite word length representation in the linear domain as well as using rounding. Results show that the proposed method naturally provides smaller approximation error compared to rounding. Furthermore, they provide insights into finite word length properties of FIR filters coefficients in the LNS domain and show that LNS FIR filters typically provide a better approximation error compared to a standard FIR filter.

show abstract

Integrated-Circuit Logarithmic Arithmetic Units

Cited by 24 publications

References 22 publications

Techniques for Efficient Implementation of FIR and Particle Filtering

Techniques for Efficient Implementation of FIR and Particle Filtering

Logarithmic arithmetic as an alternative to floating-point: A review

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Contact Info

Product

Resources

About