Integrated CPU-GPU Power Management for 3D Mobile Games

Pathania, Anuj; Jiao, Qing; Prakash, Alok; Mitra, Tulika

doi:10.1145/2593069.2593151

Cited by 128 publications

(91 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [15], multi-component DVFS algorithm is proposed by considering the data and control flow of IPs in the SoC. Pathania et al proposed a CPU-GPU coordinated DVFS technique for 3D mobile game applications [16]. For efficient runtime power/energy management, Linux provides various policies considering the application loads [17].…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Kong

Lee

2017

IEICE Electron. Express

View full text Add to dashboard Cite

Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management. However, adoption of system-level cache under DVFS-enabled CPU may incur abnormal cache hierarchy (i.e., a delay reversal between the highlevel and low-level caches). It may lead to performance-and energyinefficiency due to slower data delivery and meaningless accesses to intermediate levels of caches. To resolve this problem, we propose a DVFS-aware cache bypassing technique. Our technique profiles latencies of the various levels of the caches. Based on the profiled information, our technique adaptively bypasses intermediate levels of caches in the case of abnormal cache hierarchy and applies power-gating to that cache memory for better energy efficiency. According to our evaluation, our technique reduces L2 and system-level cache energy consumption by up to 14.5% while improving performance by up to 0.13% compared to the baseline.

show abstract

Section: Related Workmentioning

confidence: 99%

“…The CPU can operate from 0.4 GHz to 2.0 GHz and one frequency step is 400 MHz while system-level cache operate at 1 GHz. Please note that DVFS in modern mobile system mainly focuses on CPU and GPU while memory-related system rather uses a fixed clock frequency [16]. Table I summarizes assumptions in our mobile CPU and system-level caches.…”

Section: Preliminariesmentioning

confidence: 99%

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Kong

Lee

2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The authors of [ML09] proposed a warp processor architecture that leverages DVFS to reduce the power consumption. The authors of [PJPM14] described an integrated power manager that exploited the DVFS capabilities of embedded CPU and GPU together. This is related to the Parameter Selection stage in Figure 2.1.…”

Section: Design Requirements 221 Energy Efficiencymentioning

confidence: 99%

Security-Driven Design of Real-Time Embedded Systems

Jiang¹

2016

View full text Add to dashboard Cite

R eal-time embedded systems (RTESs) have been widely used in modern society. And it is also very common to find them in safety and security critical applications, such as transportation and medical equipment. There are, usually, several constraints imposed on a RTES, for example, timing, resource, energy, and performance, which must be satisfied simultaneously. This makes the design of such systems a difficult problem.More recently, the security of RTESs emerges as a major design concern, as more and more attacks have been reported. However, RTES security, as a parameter to be considered during the design process, has been overlooked in the past. This thesis approaches the design of secure RTESs focusing on aspects that are particularly important in the context of RTES, such as communication confidentiality and side-channel attack resistance.Several techniques are presented in this thesis for designing secure RTESs, including hardware/software co-design techniques for communication confidentiality on distributed platforms, a global framework for secure multi-mode real-time systems, and a scheduling policy for thwarting differential power analysis attacks.All the proposed solutions have been extensively evaluated in a large amount of experiments, including two real-life case studies, which demonstrate the efficiency of the presented techniques.The research presented in this thesis has been funded by CUGS (the National Graduate School in Computer Science in Sweden) and VR (the Swedish Research Council).v Populärvetenskaplig Sammanfattning I nbyggda realtidssystem används idag i stor utsträckning i vårt moderna samhälle. Detär mycket vanligt att hitta dem i säker-hetskritiska tillämpningar såsom transport-och medicinsk utrustning. Vanligtvis har inbyggda realtidssystem flera designbegränsningar och krav gällande till exempel timing, resurser, energi och prestanda, som måste vara uppfyllda samtidigt. Detta gör utformningen av sådana system till ett mycket svårt problem.Under senare tid har säkerheten i inbyggda realtidssystem blivit en viktig konstruktionsaspekt eftersom fler och fler attacker har rapporterats. Tidigare har säkerhetskraven i inbyggda realtidssystem inte betraktats som designparametrar under själva designprocessen. Denna avhandling fokuserar bland annat på utformningen av säkra inbyggda system, huvudsakligen på aspekter somär särskilt viktiga i samband med realtidssystem, till exempel kommunikationssekretess och motstånd mot sidokanalattacker.I denna avhandling presenteras tre olika tekniker för att utforma säkra inbyggda realtidssystem. Först en teknik för hård-och mjukvaru co-design för kommunikationssekretess för distribuerade plattformar, sedan ett globalt ramverk för säkra multi-mode system och slutligen en schemaläggningspolicy för motstånd mot sidokanalattacker.Samtliga de föreslagna lösningarna har utvärderats i stor omfattning med en stor mängd experiment, inklusive två fallstudier som visar effektiviteten hos de presenterade teknikerna.vii

show abstract

“…The Process Cruise Control framework [44] and the Koala framework [45] adjust the CPU performance for given workloads according to the workloads characteristics captured with performance counters. Pathania et al adjust the performance point of CPU and GPU together according to 3D game workloads history to save energy [46]. Gupta et al point out that the power consumed by uncore components, e.g., memory controller, should be considered in making runtime PM decisions for the CPU [47].…”

Section: Related Workmentioning

confidence: 99%

Automated OS-level Device Runtime Power Management

Lin²,

Wang

et al. 2015

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

Non-CPU devices on a modern system-on-a-chip (SoC), ranging from accelerators to I/O controllers, account for a significant portion of the chip area. It is therefore vital for system energy efficiency that idle devices can enter a lowpower state while still meeting the performance expectation. This is called device runtime Power Management (PM) for which individual device drivers in commodity OSes are held responsible today. Based on the observations of existing drivers and their evolution, we consider it harmful to rely on drivers for device runtime PM.This paper identifies three pieces of information as essential to device runtime PM, and shows that they can be obtained without involving drivers, either by using a softwareonly approach, or more efficiently, by adding one register bit to each device. We thus suggest a structural change to the current Linux runtime PM framework, replacing the PM code in all applicable drivers with a single kernel module called the central PM agent. Experimental evaluations show that the central PM agent is just as effective as hand-tuned driver PM code. The paper also presents a tool called PowerAdvisor that simplifies driver PM efforts under the current Linux runtime PM framework. PowerAdvisor analyzes execution traces and suggests where to insert PM calls in driver source code. Despite being a best-effort tool, PowerAdvisor not only reproduces hand-tuned PM code from stock drivers, but also correctly suggests PM code never known before. Overall, our experience shows that it is promising to ultimately free driver developers from manual PM.

show abstract

Integrated CPU-GPU Power Management for 3D Mobile Games

Cited by 128 publications

References 14 publications

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Security-Driven Design of Real-Time Embedded Systems

Automated OS-level Device Runtime Power Management

Contact Info

Product

Resources

About