Integrated Cryo-CMOS Temperature Sensors for Quantum Control ICs

Hart, Pascal A. lt; Huizinga, T.; Babaie, Masoud; Vladimirescu, Andrei; Foti, Sebastiano

doi:10.1109/wolte55422.2022.9882600

Cited by 7 publications

(6 citation statements)

References 12 publications

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“…Finally, the resistors that are required for most references also suffer from a temperature dependence. To minimize these effects, n-type unsilicided poly resistors will be used, which vary less than 5% over temperature [28]. Furthermore, the reference voltage will mostly be set by a ratio of resistors, hence making it less vulnerable to changes in absolute resistance.…”

Section: Cryo-cmos Design Challengesmentioning

confidence: 99%

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

van Staveren,

Padalia,

Charbon

et al. 2024

IEEE J. Solid-State Circuits

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This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in weak inversion to achieve continuous operation from room temperature (RT) down to cryogenic temperatures. Their accuracy limitations due to curvature, body effect, and mismatch are investigated and experimentally validated. Implemented in 40-nm CMOS, the references show a line regulation better than 2.7%/V from a supply as low as 0.99 V. By applying dynamic element matching (DEM) techniques, a spread of 1.2% (3σ ) from 4.2 to 300 K can be achieved, resulting in a temperature coefficient (TC) of 111 ppm/K. As the first significant statistical characterization extending down to cryogenic temperatures, the results demonstrate the ability of the proposed architectures to work under cryogenic harsh environments, such as space-and quantumcomputing applications.

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Section: Cryo-cmos Design Challengesmentioning

confidence: 99%

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

van Staveren,

Padalia,

Charbon

et al. 2024

IEEE J. Solid-State Circuits

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“…Applying FBB via the bulk contact may be potentially limited by the high substrate resistance at cryogenic temperature, as indicated by typical N-well resistances up to a few G /□ at 4.2 K [29], [30]. If such large bulk resistance (R B in Fig.…”

Section: Limitations Of Cryogenic-aware Fbbmentioning

confidence: 99%

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

Kiene,

Overwater,

Babaie

et al. 2024

IEEE Trans. Circuits Syst. I

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This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2× time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sampleand-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR=38.7 dB (38.2 dB), SFDR>50 dB (>50 dB), and FOM W =25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively.

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“…For implementation of all resistors on this work, we used unsilicided n-type polysilicon due to its stability at cryogenic temperatures. In [43], a change in resistance of ≈5% was measured between cryogenic and RT.…”

Section: A Cyrogenic Circuit Designmentioning

confidence: 99%

A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

Kiene

Overwater

Catania

et al. 2023

IEEE J. Solid-State Circuits

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This article presents a two-times interleaved, loopunrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM W ) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/convstep (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.

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Integrated Cryo-CMOS Temperature Sensors for Quantum Control ICs

Cited by 7 publications

References 12 publications

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing

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