Integrated Fiber-Optic Receivers

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

“…Its key advantages are its wide linear range and the fact that it incorporates the decision circuit, thus resulting self-aligned, that is, when the PLL is in lock the clock signal is automatically set in the center of the data eye to be sampled. However, it has to be noted that self-aligned PD architectures at high frequency suffer from the effect of finite transit times of D-type flip-flop circuits, so that a nonzero static phase error is present, and data-clock alignment at the decision circuit relies on delay matching between different paths, thus reducing jitter tolerance [17]- [19]. In recent applications, often a separate decision circuit is used, to allow a better optimization of circuit parameters [11].…”

High-Frequency Oscillator Design for Integrated Transceivers

“…However, as indicated by the lowpass curve in the symbols of transconductances 6 8m,, these are modeled with a single-pole model: 8m,/(l + jw-r 1 ). In many practical cases, ring oscillator stage implementation satisfy dominant pole behavior [101,102], and the reduced order of a single-pole model can 5 However with respect to phase noise performance normalized for power, the multi-phase LC oscillator has, no advantage compared to a single-phase LC oscillator: seep. 151.…”

“…A detailed twointegrator design example is given in Chapter 9. For N-stage ring oscillators, a reasonable estimate of the oscillation frequency can be written as [101] fMAX Jose ~ 2 N ,…”

“…This means that the DCR circuit must be able to acquire phase lock with the clock signal from the random data. Many advanced integrated DCR circuits are PLL based [101]. Since the free-running frequency of the oscillator in the PLL is never exactly the same as the incoming data rate, the DCR circuit must obtain frequency lock prior to phase lock.…”

“…Since the free-running frequency of the oscillator in the PLL is never exactly the same as the incoming data rate, the DCR circuit must obtain frequency lock prior to phase lock. In practice this means that every PLL-based DCR circuit needs some type of frequency acquisition aid [101]. One option is to use a crystal oscillator to keep the oscillator frequency within the acquisition range of the PLL, but this solution requires an expensive external crystal and an IC pin.…”