Integrated multi-band RF transceiver design for multi-standard applications using 130 ​nm CMOS technology

Mansour, Marwa; Zekry, Abdelhalim; Ali, Mohammed K.; Shawkey, Heba

doi:10.1016/j.mejo.2021.105006

Cited by 20 publications

(4 citation statements)

References 8 publications

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“…e PWM modulator in the nRF24E1 chip has a maximum carrier frequency of 64 KHz, which makes data reception easier to filter. e system's man-machine interface function is realized by the keyboard and LCD display screen [7]. e instruction system of the nRF24E1 microprocessor is compatible with the industry standard 8051 instruction system, but the instruction execution time of the two is somewhat different.…”

Section: Wireless Radio Frequency Transceiver Chip Nrf24e1mentioning

confidence: 99%

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Liu

2021

International Journal of Antennas and Propagation

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A Chinese-English wireless simultaneous interpretation system based on speech recognition technology is suggested to solve the problems of low translation accuracy and a high number of ambiguous terms in current Chinese-English simultaneous interpretation systems. The system’s general structure and hardware architecture are summarized. The chairman unit, representative unit, transliteration unit, and auditing unit are the four basic components of the simultaneous interpretation system. The CPU is the nRF24E1 hardware wireless radio frequency transceiver chip, while the chairman machine, representative machine, translator, and auditorium are all created separately. Speech recognition technology is used by the system software to create a speech recognition process that properly produces speech-related semantics. The input text is used as the search criteria, a manual interactive synchronous translation program is created, and the results for the optimum translation impact are trimmed. The experimental findings reveal that this system’s sentence translation accuracy rate is 0.9–1.0, and the number of ambiguous terms is minimal, which is an improvement on previous systems’ low translation accuracy.

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Section: Wireless Radio Frequency Transceiver Chip Nrf24e1mentioning

confidence: 99%

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Liu

2021

International Journal of Antennas and Propagation

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“…The link budget parameters' 33 computation is illustrated in Table 1. This table defines the required output power, hence helping in the transistor size chosen in implementing the transformer‐coupled power amplifier.…”

Section: Power Amplifier Analysis and Designmentioning

confidence: 99%

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Mansour

2022

Circuit Theory & Apps

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High‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively.

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“…In 2020, different filters were used in a 4 × 4 dual band Wi-Fi 802.11ax transceiver proposed by E. Lu, et al A second order baseband filter was used in the TX mode with an I/Q transimpedance amplifier, followed by a programmable second order Butterworth opamp-RC filter/programmable gain amplifier (PGA) used in the RX mode [9]. In 2021, a radio frequency (RF) transmitter architecture proposed by M. Mansour, et al showed that the low-pass filter (LPF) and the variable gain amplifier (VGA) of the receiver were used in the RX mode, while the LPF-transmitter and the PGA-transmitter were used in the TX mode [10]. The area of the chip determines its price; a smaller area is the key specification for chip competitiveness.…”

Section: Introductionmentioning

confidence: 99%

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

Wang

2022

Electronics

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The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and −10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/√ Hz, while the IRN of the IF-transmitter at 10 MHz BW and -6 dB gain is 95.16 nV/√ Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm2.

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Integrated multi-band RF transceiver design for multi-standard applications using 130 nm CMOS technology

Cited by 20 publications

References 8 publications

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

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Integrated multi-band RF transceiver design for multi-standard applications using 130 ​nm CMOS technology

Cited by 20 publications

References 8 publications

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Design of Chinese-English Wireless Simultaneous Interpretation System Based on Speech Recognition Technology

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

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Integrated multi-band RF transceiver design for multi-standard applications using 130 nm CMOS technology