Integrating adaptive on-chip storage structures for reduced dynamic power

Dropsho, Steven; Buyuktosunoglu, Alper; Balasubramonian, Rajeev; Albonesi, David H.; Dwarkadas, Sandhya; Semeraro, Greg; Magklis, Grigorios; Scott, Michael L.

doi:10.1109/pact.2002.1106013

Cited by 80 publications

(134 citation statements)

References 21 publications

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“…In the load / store domain, the adaptive L1 DCache and L2 cache are up to eightway set associative, and resized by ways [2,8]. This provides a wide range of sizes to accommodate a wide variation in workload behavior.…”

Section: Resizable Cachesmentioning

confidence: 99%

“…To control the reconfigurable caches, we employ the Accounting Cache algorithm previously applied to improving cache energy efficiency [8]. Due to the fact that the smaller configurations are subsets of the larger ones, the algorithm is able to collect statistics for all possible configurations simultaneously.…”

Section: Phase Adaptive Cache Control Algorithmmentioning

confidence: 99%

“…As described in detail in previous work [8], the Accounting Cache maintains full most-recently-used (MRU) state on cache lines. Simple counts of the number of blocks accessed in each MRU state are sufficient to reconstruct the precise number of hits and misses to the A and B partitions for all possible cache configurations, regardless of the current configuration.…”

Section: Phase Adaptive Cache Control Algorithmmentioning

confidence: 99%

“…Our work highly leverages the Accounting Cache research of [8] and the adaptive GALS processor design of [9]. The latter effort uses the Accounting Cache within an MCD processor design much like we do.…”

Section: Related Workmentioning

confidence: 99%

“…The addition of a second running thread often puts more demand on cache capacity, and this greater demand is met by dynamically upsizing the cache. We adopt the Accounting Cache design of [8] for our resizable caches.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

López

Dropsho

Albonesi

et al. 2007

High Performance Embedded Architectures and Compilers

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Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeoff. This problem is exacerbated in a Simultaneous Multi-Threaded (SMT) processor where the optimal cache design may vary drastically with the number of running threads and their characteristics.We propose to make this capacity-speed cache tradeoff dynamic within an SMT core. We extend a previously proposed globally asynchronous, locally synchronous (GALS) processor core with multi-threaded support, and implement dynamically resizable instruction and data caches. As the number of threads and their characteristics change, these adaptive caches automatically adjust from small sizes with fast access times to higher capacity configurations. While the former is more performance-optimal when the core runs a single thread, or a dual-thread workload with modest cache requirements, higher capacity caches work best with most multiple thread workloads. The use of a GALS microarchitecture permits the rest of the processor, namely the execution core, to run at full speed irrespective of the cache speeds. This approach yields an overall performance improvement of 24.7% over the best fixed-size caches for dual-thread workloads, and 19.2% for single-threaded applications.

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Section: Resizable Cachesmentioning

confidence: 99%

Section: Phase Adaptive Cache Control Algorithmmentioning

confidence: 99%

Section: Phase Adaptive Cache Control Algorithmmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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