Integrating ADC using a single transistor as integrator and amplifier for very low (1 fA minimum) input currents

Uster, M.; Loeliger, T.; Guggenbühl, W.; Jäckel, H.

doi:10.1049/cp:19990470

Cited by 8 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Power saving is usually achieved by reducing the supply voltage. While supply voltage reduction is currently limited to some tenths of volts, favorably, circuits operating with currents as low as femtoamperes are reported so far [3][4][5][6][7][8]. Comparing limited supply voltage reduction capability with the remarkably large reduction factor obtainable for the currents, it is concluded that by reducing the circuit's currents, much smaller power consumption can be achieved.…”

Section: Bias Circuit and Nanocurrent Source Arraysmentioning

confidence: 99%

“…So far, power reduction techniques mostly concentrate on reduction of voltages, but the extent of voltage reduction is narrow and cannot result to noticeable power reduction. Meanwhile, the current can be reduced to nanovalues and beyond (femto and atto) [3,4], promising extra significant reduction in power down to nanowatts and less [5]. These methods thus deserve much more approach as such in this paper.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV

2012

View full text Add to dashboard Cite

In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on nanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a widely used consumer appliance, it is aimed to be such designed to consume power as low as possible. Hence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the bits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to establish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V, resulting to an ultralow power of 52.9 μW. Many other powerful ideas are then deliberately combined to maintain both high speed and very low glitches required for HDTV application despite those ultralow currents and power. The result is a speed of 100 MS/s, an ultralow glitch of ≃10.91 fAs, |INL| ≤ 0.988 LSB, |DNL| ≤ 0.99 LSB, and a spurious-free dynamic range of ≃73 dB. These results caused the proposed DAC to execute a distinguished overall performance (defined as figure of merit) greatly better than some other advanced ones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-μm complementary metal-oxide semiconductor technology have been used to validate the proposed circuit. Performance evaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature variations proved both its well mismatch insensitivity and thermal stability.

show abstract

Section: Bias Circuit and Nanocurrent Source Arraysmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV

2012

View full text Add to dashboard Cite

show abstract

“…Recently, application of CMOS femto-ampère current-mode circuits in cases such as research and production of biosensors, data convertors, ion mobility sensors, detectors, ultra-low-current processors and design and manufacturing measurement instruments has been highly demanding [12,[14][15][16][17][18][20][21][22]. Biasing MOSFETs in weak inversion is very useful also in nonlinear applications such as the design of exponential trans-conductors, which provides pico-ampère at simulation level, as already discussed in [8].…”

Section: Introductionmentioning

confidence: 99%

A Novel Ultra-Low-Power Low-Voltage Femto-Ampère Current Mirror

Monfaredi

Baghtash

Azhari

2011

Circuits Syst Signal Process

View full text Add to dashboard Cite

A novel femto-ampère current mirror/negative impedance converter (FACMNIC) is proposed in this paper. It is shown that extremely large output impedance approaching infinite value and also negative impedances of different values can be remarkably obtained just by adjusting the built-in positive feedback loop gain. Operation of this circuit is based on two approaches called here as source voltage shifting and channel conduction manipulation. Although those two techniques are briefly explained in this paper but due to their strong action worth extensively studying and exercising. Deliberately having been composed of both current mirror and negative impedance converter capabilities in the same structure causes the proposed circuit to have a simple structure prohibiting large chip area consumption while favorably preserves following unique features. At 0.9 volt power supply it produces very small currents down to 4.6 fA and consumes an ultra-low power of 86 nW, thus it is the best choice for Ultra-Low-Power Low-Voltage (ULPLV) applications. It also exhibits the outstanding high output impedance of 400 G when it is optimized for best performance operation, otherwise it can be adjusted so as to produce very high output impedances (approaching infinite values). Due to the inclusion of positive feedback, Monte Carlo analyses are performed to ensure the stability and robustness of the circuit's operation in the presence of the PVT (process, voltage and temperature) variations. Simulation results in TSMC 0.18 µm CMOS technology

show abstract

“…An integrating 64-channel ADC was proposed in [7] which has a 16-bit resolution; however, it consumes *4 mW per channel at a sample rate of approximately 80 Hz. Power consumption will increase significantly for this topology as the sampling rate increases.…”

Section: Introductionmentioning

confidence: 99%

A novel current-mode multi-channel integrating ADC

Nambiar

Blalock

Ericson

2009

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

A novel current-mode multi-channel ADC has been designed, fabricated, and characterized in a 0.5-lm bulk CMOS process. The ADC utilizes a Wilkinson architecture with current-mode comparators and is capable of supporting multiple channels with an input current range of 10-150 lA. The main blocks in the ADC include a current ramp generator with active current mirrors, multiple current comparators, and a 12-bit Gray code counter. A novel architecture Gray code counter supports high frequency counting. For sampling rates up to 10 kHz, measurement results are presented including integral nonlinearity and differential nonlinearity. A per-channel power consumption of less than 2 mW using a Wilkinson architecture with 4 channels was observed. This work represents the first published current-mode, multi-channel Wilkinson ADC.

show abstract

Integrating ADC using a single transistor as integrator and amplifier for very low (1 fA minimum) input currents

Cited by 8 publications

References 7 publications

A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV

A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV

A Novel Ultra-Low-Power Low-Voltage Femto-Ampère Current Mirror

A novel current-mode multi-channel integrating ADC

Contact Info

Product

Resources

About