Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim

Farshchi, Farzad; Huang, Qijing; Yun, Heechul

doi:10.1109/emc249363.2019.00012

Cited by 45 publications

(14 citation statements)

References 10 publications

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“…Our framework does not target an FPGA-accelerated environment such as Firesim [21]. FireSim has also been integrated with the NVDLA accelerator [14], which requires editing the RTL code of the SoC. gem5+rtl is less accurate at the entire SoC level, but in exchange it offers more flexibility with a generic full-system simulator that is easier to modify and work with.…”

Section: Fpga-accelerated Solutionsmentioning

confidence: 99%

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

López-Paradís

Armejach

Moretó

2021

50th International Conference on Parallel Processing

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In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system in which the design will operate. This hinders proper testing and debugging of functionalities, and does not allow co-designing the accelerator to obtain a balanced and efficient architecture.In this paper, we introduce gem5+rtl, a flexible framework that enables simulation of RTL models inside a full-system software simulator. We present the framework's functionality that allows easy integration of RTL models on a simulated system-on-chip (SoC) that is able to boot Linux and run complex multi-threaded and multi-programmed workloads. We demonstrate the framework with two relevant use cases that integrate a multi-core SoC with a Performance Monitoring Unit (PMU) and the NVIDIA Deep Learning Accelerator (NVDLA), showcasing how the framework enables testing RTL model features and how it can enable co-design taking into account the entire SoC.

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Section: Fpga-accelerated Solutionsmentioning

confidence: 99%

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

López-Paradís

Armejach

Moretó

2021

50th International Conference on Parallel Processing

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“…Work in this area can be partitioned into two subareas, roughly along the dimension of generality. The first, and more general, involves the design and testing of domain-specific accelerators (e.g., GEMM accelerators such as Gemmini [43] and NVDLA [47]) as custom instruction set architectures (ISAs). These ISAs are conceptually not so different from general-purpose compute architectures (in that they are programmable) except insofar as they prioritize a limited number of operations, particularly those pertinent to AI workloads (such as matrix multiplication).…”

Section: Lightweight Ai Capability For Future Detector Systemsmentioning

confidence: 99%

A Hardware Co-design Workflow for Scientific Instruments at the Edge

Yoshii¹,

Sankaran²,

Strempfer³

et al. 2021

Preprint

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As spatial and temporal resolutions of scientific instruments improve, the explosion in the volume of data produced is becoming a key challenge. It can be a critical bottleneck for integration between scientific instruments at the edge and high-performance computers/emerging accelerators. Placing data compression or reduction logic close to the data source is a possible approach to solve the bottleneck. However, the realization of such a solution requires the development of custom ASIC designs, which is still challenging in practice and tends to produce one-off implementations unusable beyond the initial intended scope. Therefore, as a feasibility study, we have been investigating a design workflow that allows us to explore algorithmically complex hardware designs and develop reusable hardware libraries for the needs of scientific instruments at the edge. Our vision is to cultivate our hardware development capability for streaming/dataflow hardware components that can be placed close to the data source to enable extreme dataintensive scientific experiments or environmental sensing. Furthermore, reducing data movement is essential to improving computing performance in general. Therefore, our co-design efforts on streaming hardware components can benefit computing applications other than scientific instruments. This vision paper discusses hardware specialization needs in scientific instruments and briefly reviews our progress leveraging the Chisel hardware description language and emerging open-source hardware ecosystems, including a few design examples.

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“…In [3] the authors presented LACore, a novel, programmable accelerator architecture for general-purpose linear algebra applications suitable for the RISC-V new generation of processor cores. In [4], the authors integrate Nvidia Deep Learning Accelerator (NVDLA) into a RISC-V SoC. NVDLA, is an open-source deep neural network (DNN) accelerator which has received a lot of attention by the research community since its introduction by Nvidia.…”

Section: Related Workmentioning

confidence: 99%

Digital Signal Processing Accelerator for RISC-V

Calicchia

Ciotoli

Cardarilli

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim

Cited by 45 publications

References 10 publications

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

A Hardware Co-design Workflow for Scientific Instruments at the Edge

Digital Signal Processing Accelerator for RISC-V

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