Abstract-High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programmer experience.In this paper, we explore the different trade-offs present when using a representative set of HLS tools in the context of Database Management Systems (DBMS) acceleration. More specifically, we conduct an empirical analysis of four representative frameworks (Bluespec SystemVerilog, Altera OpenCL, LegUp and Chisel) that we utilize to accelerate commonly-used database algorithms such as sorting, the median operator, and hash joins. Through our implementation experience and empirical results for database acceleration, we conclude that the selection of the most suitable HLS depends on a set of orthogonal characteristics, which we highlight for each HLS framework.

large shared-memory multi-core configurations [16,28,35]. For example, OpenMP, the most popular approach for shared memory programming, has significantly evolved and currently incorporates advanced features such as tasking support [4,39]. For all these reasons, parallel operations such as scheduling and synchronization are expected to become key system software components. As a result, simulators targeting nextgeneration HPC systems must take into account such parallel operations performed at the runtime system level.Existing tools make simulation of large-scale HPC machines with thousands of cores unfeasible. Conventional cycleaccurate architectural simulators offer a great level of detail, but make simulation times impractical when using more than a few tens [6,7,51] or a few hundreds of cores [45]. Higherlevel simulators are able to simulate thousands of cores at the cost of not modelling any microarchitectural details or the impact of the system software [2,14,55]. Raising the level of abstraction is necessary, but needs to be done to an appropriate degree. Hence, it is critical to develop flexible simulation infrastructures that allow to quickly trim the vast design space while still capturing the impact of the simulated microarchitecture and system software.In this paper we make the following contributions:• We present MUSA, a multi-scale simulation approach that enables fast and accurate performance estimations of next-generation HPC machines. Our methodology seamlessly captures inter-node communication as well as intranode microarchitectural and system software interactions, improving usability and simplifying the simulation workflow. MUSA relies on native execution traces with two levels of detail to allow simulation of different communication networks, numbers of cores per node, and relevant microarchitectural parameters. • We validate MUSA using the NAS Multi-Zone ParallelBenchmark suite [27], and then evaluate three large-scale case studies (with up to 16,384 cores) using BT-MZ, HYDRO [33], and SPECFEM3D [31]. Our evaluation shows that MUSA provides accurate performance predictions by combining information at different levels of granularity. When comparing native executions and MUSA simulations with up to 2,048 cores, we achieve relative errors within 10% in the common case, demonstrating that our detailed model is able to capture microarchitectural and system software effects. In addition, we show that our simulations complete in an affordable amount of Abstract-The complexity of High Performance Computing (HPC) systems is increasing in the number of components and their heterogeneity. Interactions between software and hardware involve many different aspects which are typically not transparent to scientific p rogrammers a nd s ystem a rchitects. Therefore, predicting the behavior of current scientific applications on future HPC infrastructures is a challenging task.In this paper we present MUSA, an end-to-end methodology that employs a multi-level simulation infrastructure. By combining different lev...

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