Stencil codes on a vector length agnostic architecture

Armejach, Adrià; Caminal, Helena; Cebrian, Juan M.; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero, Mateo; Casas, Marc; Moretó, Miquel

doi:10.1145/3243176.3243192

Cited by 20 publications

(15 citation statements)

References 19 publications

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“…Furthermore, the constant for the multiplication (line 12) and the stencil instructions (line 14) are sent to the SPU. The streams for all the SPU are configured inside the loop (lines [22][23][24][25][26][27][28][29]. In this example, four streams are configured: three input streams to load the elements at A…”

Section: An Example: Jacobi-2d Stencilmentioning

confidence: 99%

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Denzler¹,

Oliveira²,

Hajinazar³

et al. 2023

IEEE Access

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Stencil computations are commonly used in a wide variety of scientific applications, ranging from largescale weather prediction to solving partial differential equations. Stencil computations are characterized by three properties: (1) low arithmetic intensity, (2) limited temporal data reuse, and (3) regular and predictable data access pattern. As a result, stencil computations are typically bandwidth-bound workloads, which only experience limited benefits from the deep cache hierarchy of modern CPUs. In this work, we propose Casper, a near-cache accelerator consisting of specialized stencil computation units connected to the last-level cache (LLC) of a traditional CPU. Casper is based on two key ideas: (1) avoiding the cost of moving rarely reused data throughout the cache hierarchy, and (2) exploiting the regularity of the data accesses and the inherent parallelism of stencil computations to increase overall performance. With minimal changes in LLC address decoding logic and data placement, Casper performs stencil computations at the peak LLC bandwidth. We show that by tightly coupling lightweight stencil computation units near LLC, Casper improves performance of stencil kernels by 1.65× on average (up to 4.16×) compared to a commercial high-performance multi-core processor, while reducing system energy consumption by 35% on average (up to 65%). Casper provides 37× (up to 190×) improvement in performance-per-area compared to a state-of-the-art GPU.

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Section: An Example: Jacobi-2d Stencilmentioning

confidence: 99%

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Denzler¹,

Oliveira²,

Hajinazar³

et al. 2023

IEEE Access

View full text Add to dashboard Cite

show abstract

“…A wide body of research has focused on studying and analyzing stencil computations [3,16,18,22,26,32,38]. PIMS [22] is the most closely-related work to Casper.…”

Section: Related Workmentioning

confidence: 99%

Casper: Accelerating Stencil Computation using Near-cache Processing

Denzler¹,

Bera²,

Hajinazar³

et al. 2021

Preprint

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Stencil computation is one of the most used kernels in a wide variety of scientific applications, ranging from large-scale weather prediction to solving partial differential equations. Stencil computations are characterized by three unique properties: (1) low arithmetic intensity, (2) limited temporal data reuse, and (3) regular and predictable data access pattern. As a result, stencil computations are typically bandwidth-bound workloads, which only experience limited benefits from the deep cache hierarchy of modern CPUs.In this work, we propose Casper, a near-cache accelerator consisting of specialized stencil compute units connected to the lastlevel cache (LLC) of a traditional CPU. Casper is based on two key ideas: (1) avoiding the cost of moving rarely reused data through the cache hierarchy, and (2) exploiting the regularity of the data accesses and the inherent parallelism of the stencil computation to increase the overall performance. With minimal changes in LLC address decoding logic and data placement, Casper performs stencil computations at the peak bandwidth of the LLC. We show that, by tightly coupling lightweight stencil compute units near to LLC, Casper improves performance of stencil kernels by 1.65× on average, while reducing the energy consumption by 35% compared to a commercial high-performance multi-core processor. Moreover, Casper provides a 37× improvement in performance-per-area compared to a state-of-the-art GPU.

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“…We also evaluate the impact of compiler auto-vectorization using the recently proposed Scalable Vector Extension (SVE) ISA [53]. SVE is vector length agnostic, meaning that a single binary can run on any target vector length [4]. Therefore, we evaluate a scalar binary and an SVE-enabled binary with vector lengths of 128, 256, and 512 bits.…”

Section: Performance Evaluationmentioning

confidence: 99%

Planar

Barredo

Armejach

Beard

et al. 2021

Proceedings of the ACM International Conference on Supercomputing

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Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with multi-core systems, (ii) hides rearrangement latency, and (iii) provides the necessary interfaces to ease programmability.In this work we present Planar, a programmable near-memory accelerator that rearranges sparse data into dense. By placing Planar devices at the memory controller level we enable a design that scales well with multi-core systems, hides operation latency by performing non-blocking fine-grain data rearrangements, and eases programmability by supporting virtual memory and conventional memory allocation mechanisms. Our evaluation shows that Planar leads to significant reductions in data movement and dynamic energy, providing an average 4.58× speedup. CCS CONCEPTS• Hardware → Memory and dense storage; • Computer systems organization → Multicore architectures; • General and reference → Performance; • Computing methodologies → Vector / streaming algorithms.

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Stencil codes on a vector length agnostic architecture

Cited by 20 publications

References 19 publications

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Casper: Accelerating Stencil Computations Using Near-Cache Processing

Casper: Accelerating Stencil Computation using Near-cache Processing

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