An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

Arcas-Abella, Oriol; Ndu, Geoffrey; Sönmez, Nehir; Ghasempour, Mohsen; Armejach, Adrià; Navaridas, Javier; Song, Wei; Mawer, John; Cristal, Adrián; Luján, Mikel

doi:10.1109/fpl.2014.6927484

Cited by 44 publications

(25 citation statements)

References 21 publications

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“…Area for a NoCG 2-lane VFU configuration is 36191, 38060, 40693, and 43419 µm 2 for 1, 2, 3, and 4 stages respectively. Area overhead is in some cases higher than expected because: (1) during synthesis, we prioritized timing and power over area to assure power savings without spoiling timing and (2) Chisel generated Verilog code is sometimes less area efficient than equivalent manually written Verilog [39]. However, we observe this overhead has a strong decreasing trend as the n S increases.…”

Section: Discussionmentioning

confidence: 70%

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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic¹,

Palomar

Stanić

et al. 2018

IEEE Trans. VLSI Syst.

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The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a functional unit with high power consumption, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and "real world" application-based benchmarking. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. Finally, when evaluating all techniques together, using "real world" benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.

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Section: Discussionmentioning

confidence: 70%

“…The Chisel code is compact, due to its higher level of description than traditional HDL. Not surprisingly, as a general problem of highlevel design approaches, a disadvantage of Chisel-based digital design is that it sometimes has worse quality of results than handcrafted Verilog [39].…”

Section: A Fully Parameterizable Fma Generatormentioning

confidence: 99%

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic¹,

Palomar

Stanić

et al. 2018

IEEE Trans. VLSI Syst.

Self Cite

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“…The array pointers passed to the FPGA are normally shared between CPU and FPGA, and the preferred option to connect the FPGA accelerator to the processing system is to use the ACP coherent port. 1 Using this approach, SDSoC automatically manages the data movement from global memory to the FPGA and back.…”

Section: Parallel_for Template and Hbb Classesmentioning

confidence: 99%

“…Bit-level parallel computing fits certain algorithms that cannot be parallelized easily with traditional methods. Recently, the traditional entry barrier of FPGA design, low-level programming languages, has started to being replaced with high-level languages such as C++ and OpenCL successfully [1]. These new programming models and the acceleration capabilities of FPGAs for certain tasks have increased the interest in computing systems that combine CPUs and FPGAs; significant efforts are done not only by FPGA manufactures but also other players such as Intel with their HARP program [2], Microsoft with their Catapult framework [3] and IBM introducing coherent ports for FPGA acceleration in OpenPower [4].…”

Section: Introductionmentioning

confidence: 99%

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

et al. 2018

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Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework B Sam Amiri with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.

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“…An example is Glacier [86], which can map streaming SQL queries into hardware circuits on FPGAs. Other studies work on the acceleration on database operators such as decompression [73], sort [6], and partitioning [133]. As mentioned before, the frameworks can support FPGA acceleration for databases in two ways, managing the hardware and provide APIs, the Centaur framework [97] is an example of leveraging these ideas for the database domain.…”

Section: Programmability Trendsmentioning

confidence: 99%

In-memory database acceleration on FPGAs: a survey

et al. 2019

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While FPGAs have seen prior use in database systems, in recent years interest in using FPGA to accelerate databases has declined in both industry and academia for the following three reasons. First, specifically for in-memory databases, FPGAs integrated with conventional I/O provide insufficient bandwidth, limiting performance. Second, GPUs, which can also provide high throughput, and are easier to program, have emerged as a strong accelerator alternative. Third, programming FPGAs required developers to have full-stack skills, from high-level algorithm design to low-level circuit implementations. The good news is that these challenges are being addressed. New interface technologies connect FPGAs into the system at mainmemory bandwidth and the latest FPGAs provide local memory competitive in capacity and bandwidth with GPUs. Ease of programming is improving through support of shared coherent virtual memory between the host and the accelerator, support for higher-level languages, and domain-specific tools to generate FPGA designs automatically. Therefore, this paper surveys using FPGAs to accelerate in-memory database systems targeting designs that can operate at the speed of main memory.

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An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

Cited by 44 publications

References 21 publications

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Simultaneous multiprocessing in a software-defined heterogeneous FPGA

In-memory database acceleration on FPGAs: a survey

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