FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.

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Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework B Sam Amiri with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.

Brushless doubly-fed induction machines (BDFIM) are attractive generators to be used in wind turbines due to the absence of brushes and slip rings. Furthermore, the BDFIM is a medium-speed generator and hence only requires one or two-stage gearbox. This feature simplifies the gearbox system and therefore improve reliability and reduce maintenance costs for the wind turbine. Although the design and operation of the BDFIM has been widely studied in the literature, there are only few studies on reliability assessment of the machine as a wind turbine generator. This paper proposes a comprehensive reliability model for two wind turbine drivetrain configurations: One with doubly-fed induction generator, and the other when the BDFIM is employed as the generator. The model is capable of evaluating the failure rate and repair rate indexes for the both configurations. Real field survey data from a 90 MW wind farm as well as calculated reliability data are then utilised to determine the reliability index values for the two drivetrain configurations in order to compare their reliability performance.

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