Integrating Through-Wafer Interconnects With Active Devices and Circuits

Jozwiak, J.; Southwick, Richard G.; Johnson, V.N.; Knowlton, William B.; Moll, Amy

doi:10.1109/tadvp.2007.906235

Cited by 16 publications

(9 citation statements)

References 21 publications

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“…where μ is the viscosity of the molten solder and w sep is the wall thickness between the holes. Using equations (1) and 4an expression for the reflow time τ can be derived:…”

Section: Pumping Timementioning

confidence: 99%

A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

Pike²,

Karl³

2009

J. Micromech. Microeng.

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Through-wafer electrical interconnection is a critical technology for advanced packaging. In this paper, a novel capillary-effect-based solder pump has been proposed and analyzed, which could produce interconnects through and between silicon dies. The principle of this pump is to use the surface tension of a molten solder, introduced in the form of balls, to drive sufficient material into a deep reactive-ion etched hole to form a through-wafer conductive path. The solder pump structure uses unwettable through-wafer holes of different diameters together with wettable metallization on two dies to provide the pressure differential and flow path. Using multiple feed holes and a single via hole complete through-wafer interconnects are demonstrated.

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“…where μ is the viscosity of the molten solder and w sep is the wall thickness between the holes. Using equations (1) and 4an expression for the reflow time τ can be derived:…”

Section: Pumping Timementioning

confidence: 99%

A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

Pike²,

Karl³

2009

J. Micromech. Microeng.

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“…At several points during the process flow, the devices were tested to ensure their continued operation. [11] Figure 5 shows the drain current as a function of drain voltage at several gate voltages for two pMOSFETs addressed from the backside of the wafer.…”

Section: Beforementioning

confidence: 99%

Through Wafer Interconnects for 3-D Packaging

2006

Self Cite

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Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.

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“…Electroplating process is then used to fill the vertical vias with metal, e.g. copper [8] - [12]. In some cases, a conductive seed layer is not applied to the via wafer, then electroplating process utilizes a sacrificial wafer bonded to the thru hole via wafer [13], [14].…”

Section: Introductionmentioning

confidence: 99%

160 Milli-Ohm Electrical Resistance Thru-Wafer Interconnects With 10:1 Aspect Ratio

Efimovskaya

Shkel

2014

International Symposium on Microelectronics

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We present a novel approach for high-aspect ratio low resistance Thru-Wafer Interconnects for Double-Sided (TWIDS) fabrication of MicroElectroMechanical Systems (MEMS). The interconnects are formed by etching blind via holes in the handle substrate of an SOI (Silicon on Insulator) wafer, followed by filling the holes with copper, using sonic-assisted seedless copper electroplating process. This technique does not require additional conductive layer deposition, but utilizes a highly doped silicon device layer as a seed. The donut-shape gaps are etched around the copper filled vias to provide interconnects insulation. We introduced the fabrication process and characterized the performance of interconnects. Experimental analysis of an array of 22 interconnects demonstrated that the resistance values as low as 160 milli-Ohm can be achieved. Parasitic capacitance of interconnects is analytically calculated and the distortion of the MEMS resonator transduction spectrum is predicted using an equivalent circuit model. Signal amplitude and phase distortion due to the parasitic capacitance are estimated to be 1.15 dB and 5.96 deg, respectively, for the optimum 60 um diameter via with 35 um insulating gap. The method presented is compatible with an in-house folded MEMS fabrication process and may enable 3D folded TIMU (Timing Inertial Measurement Unit) structures with thru-wafer interconnects.

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Integrating Through-Wafer Interconnects With Active Devices and Circuits

Cited by 16 publications

References 21 publications

A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection

Through Wafer Interconnects for 3-D Packaging

160 Milli-Ohm Electrical Resistance Thru-Wafer Interconnects With 10:1 Aspect Ratio

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