2010 IEEE International Interconnect Technology Conference 2010
DOI: 10.1109/iitc.2010.5510728
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Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

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Cited by 22 publications
(6 citation statements)
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“…11 presents simulation results of the total 3D asynchronous link, under typical conditions (Vdd=1.2V, Vcc=0.6V). Typical TSV capacitance was assumed [9], and the switches sized accordingly. This back and forth conversion to single TSV ternary adds two delays to a regular QDI data transfer: 250ps from Ai to Ao (or Bi to Bo) and 360ps from Acko to Acki, in typical conditions.…”
Section: Transmittermentioning
confidence: 99%
“…11 presents simulation results of the total 3D asynchronous link, under typical conditions (Vdd=1.2V, Vcc=0.6V). Typical TSV capacitance was assumed [9], and the switches sized accordingly. This back and forth conversion to single TSV ternary adds two delays to a regular QDI data transfer: 250ps from Ai to Ao (or Bi to Bo) and 360ps from Acko to Acki, in typical conditions.…”
Section: Transmittermentioning
confidence: 99%
“…In this paper, we integrate circuit-level P-SN estimation, system level thermal evaluation and workload assignment together effectively. Our contributions are listed as follows: [10] consider both PSN effect and thermal issue for 3D MPSoCs from the workload assignment perspective.…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, Si interposer technology is facing some challenges with regard to thermal mechanical reliability and electrical reliability [15][16][17]. One of the key concerns with regard the electrical reliability is the TSV leakage current, which causes excess Joule heat and unexpected RC paths (leading to subsequent thermal issues and signal delay) [18].…”
Section: Introductionmentioning
confidence: 99%