Integration of a Piezoelectric Layer on Si FinFETs for Tunable Strained Device Applications

Kaleli, B.; Hueting, R.J.E.; Nguyen, Minh D.; Wolters, R.A.M.

doi:10.1109/ted.2014.2316164

Cited by 12 publications

(9 citation statements)

References 25 publications

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“…In recent years, a lot of advanced architectures have emerged as potential candidates for new generation of integrated circuits for various applications such as neuron computing, including three dimentional (3-D) integration 1 – 3 , quantum cellular automata 4 – 8 , defect tolerant architecture 9 , 10 , molecular architecture and quantum computing 11 – 13 . However, they all have some limitations for use in the large scale circuits.…”

Section: Introductionmentioning

confidence: 99%

Realization of tunable artificial synapse and memory based on amorphous oxide semiconductor transistor

Dai

Wang

et al. 2017

Sci Rep

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Recently, advanced designs and materials emerge to study biologically inspired neuromorphic circuit, such as oxide semiconductor devices. The existence of mobile ions in the oxide semiconductors could be somewhat regarded to be similar with the case of the ions movements among the neurons and synapses in the brain. Most of the previous studies focus on the spike time, pulse number and material species: however, a quantitative modeling is still needed to study the voltage dependence of the relaxation process of synaptic devices. Here, the gate pulse stimulated currents of oxide semiconductor devices have been employed to mimic and investigate artificial synapses functions. The modeling for relaxation process of important synaptic behaviors, excitatory post-synaptic current (EPSC), has been updated as a stretched-exponential function with voltage factors in a more quantitative way. This quantitative modeling investigation of representative synaptic transmission bias impacts would help to better simulate, realize and thus control neuromorphic computing.

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Section: Introductionmentioning

confidence: 99%

Realization of tunable artificial synapse and memory based on amorphous oxide semiconductor transistor

Dai

Wang

et al. 2017

Sci Rep

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“…For the NC-FET, on the other hand, this strongly depends on the device architecture, though a high

is essential. Of course, materials such as HZO are more compatible in state-of-the-art CMOS technologies, but, for example, PZT can also be integrated in silicon technology, as adopted in Fe-RAM [ 18 ], or providing a proper buffer layer is used [ 48 ]. This discussion has been summarized in Table 3 .…”

Section: Discussionmentioning

confidence: 99%

“…For the first time, in collaboration with the company SolMateS B.V. (Enschede, The Netherlands), we had realized a prototype of the

-FET comprising an Si FinFET wrapped around by (buffered) PZT (see Figure 6 ) or AlN as a

-material [ 48 ]. That work resulted in several new insights.…”

Section: The Piezoelectric Field-effect Transistormentioning

confidence: 99%

“…We also measured the

-response with the laser Doppler vibrometer [ 48 ], for the two

-materials (PZT:

= 110∼110 pm/V, AlN:

= ∼13 pm/V), indicating that the devices function well electromechanically. However, for an improved performance, the device should have been covered with a mechanically rigid layer to prevent mechanical energy losses in addition to the use of less, ultrathin and stiff interfacial layers.…”

Section: The Piezoelectric Field-effect Transistormentioning

confidence: 99%

“…However, for an improved performance, the device should have been covered with a mechanically rigid layer to prevent mechanical energy losses in addition to the use of less, ultrathin and stiff interfacial layers. Furthermore, as discussed earlier [ 48 ], the conformality of the

-layer around the fin should be improved.…”

Section: The Piezoelectric Field-effect Transistormentioning

confidence: 99%

See 2 more Smart Citations

The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Hueting

2018

Micromachines

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For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π-FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., “hard” ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π-FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π-FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.

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CMOS and Beyond CMOS: Scaling Challenges

Kuhn

2018

High Mobility Materials for CMOS Applications

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Integration of a Piezoelectric Layer on Si FinFETs for Tunable Strained Device Applications

Cited by 12 publications

References 25 publications

Realization of tunable artificial synapse and memory based on amorphous oxide semiconductor transistor

Realization of tunable artificial synapse and memory based on amorphous oxide semiconductor transistor

The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

CMOS and Beyond CMOS: Scaling Challenges

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