Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Goossens, Gert; Lanneer, D.; Pauwels, Marc; Depuydt, Francis; Schoofs, Koen; Kifli, Augusli; Cornero, Marco; Petroni, Paolo; Catthoor, Francky; Man, H. De

doi:10.1007/bf02406470

Cited by 16 publications

(7 citation statements)

References 29 publications

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“…Examples of such high-level synthesis tools can be found in [21][137] [135]. They include general purpose processor synthesis [22][99], low, medium and high throughput digital signal processing [14] [54][87] [100], telecommunication applications [ 106] [ 114], controllers [ 145] [ 130], etc. High level synthesis has recently become commercially available in some domains, [12] for example gives an overview of design tools and methodologies for DSP systems.…”

Section: Hardware Design For Embedded Systemsmentioning

confidence: 99%

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Embedded system design

Camposano

Wilberg²

1996

Des Autom Embed Syst

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In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation. Verilog, VHDL and C/C++ frontends. Hardware generation in VHDL and BLIF, a retargetable compiler back-end and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts

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Section: Hardware Design For Embedded Systemsmentioning

confidence: 99%

“…For this project, a VLIW processor architecture was used and the retargetable compiler of the MOVE system. A VLIW architecture offers significant advantages for signal processing applications [54]. It relies on the compiler to perform all dependency checks and all the scheduling.…”

Section: Matrix_butterfly_dctmentioning

confidence: 99%

Embedded system design

Camposano

Wilberg²

1996

Des Autom Embed Syst

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“…This further stresses the importance of the code-generation problem. Ptolemy [Buck et al 1991;Pino et al 1995]; Flexware [Paulin et al 1995]; and Cathedral 2ND [Goossens et al 1995] are all representative examples of software synthesis and codegeneration systems targeted towards DSP applications.…”

Section: Introductionmentioning

confidence: 99%

Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining

Cheng

Lin

1999

ACM Trans. Des. Autom. Electron. Syst.

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We propose a microcode-optimizing method targeting a programmable DSP processor. Efficient generation of microcodes is essential to better utilize the computation power of a DSP processor. Since most state-of-the-art DSP processors feature some sort of irregular architectures and most DSP applications have nested loop constructs, their code generation is a nontrivial task. In this paper, we consider two features frequently found in contemporary DSP processors -structural pipelining and heterogeneous registers. We propose a code generator that performs instruction scheduling and register allocation simultaneously. The proposed approach has been implemented and evaluated using a set of benchmark core algorithms. Simulation of the generated codes targeted towards the TI TMS320C40 DSP processor shows that our system is indeed more effective compared with a commercial optimizing DSP compiler.

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“…Another, equivalent, linear formulation of the problem looks like this: for j=l..n,,, -1: for k=j+l..n,,,: k = j + l (9) q=1 with d j , k , p j = 0, 1 and (Y a large constant, greater than 2 . maz(Ci).…”

Section: The Cost-functionmentioning

confidence: 98%

“…The work described in this paper is part of the CATHEDRAL-2nd high-level synthesis system presented in [9]. …”

Section: Introductionmentioning

confidence: 99%

Signal type optimisation in the design of time-multiplexed DSP architectures

Schoofs

Goossens

Man

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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When the specifications of a DSP-algorithm are made, the minimal word lengths for all signals in order to get results with acceptable accuracy, are determined. These word lengths have' an influence on the size of the interconnection hardware in thefinal design which is often ignored in the original speci$cation of the DSP-algorithm. An algorithm is presented to modify the types of the signals to match the size of the hardware they are mapped upon. The target is to minimise the cost of multiplexers and interconnect, requiredfor various type changes. The transformation allows to modify the bit-true behaviour of the system.

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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures

Cited by 16 publications

References 29 publications

Embedded system design

Embedded system design

Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining

Signal type optimisation in the design of time-multiplexed DSP architectures

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