Proceedings of the 1998 Second IEEE International Caracas Conference on Devices, Circuits and Systems. ICCDCS 98. On the 70th A
DOI: 10.1109/iccdcs.1998.705823
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Integration of multi-level copper metallization into a high performance sub-0.25 μm CMOS technology

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“…The effect of such an intra-die variation is twofold. a) Excessive topography generated on any metal layer can lead to copper residue on the subsequent layers and a resultant yield loss due to intra-level shorts [4], [5]. b) The systematic variation in the conductor sheet resistance presents a unique problem to designers in simulating circuit behavior.…”
Section: Introductionmentioning
confidence: 99%
“…The effect of such an intra-die variation is twofold. a) Excessive topography generated on any metal layer can lead to copper residue on the subsequent layers and a resultant yield loss due to intra-level shorts [4], [5]. b) The systematic variation in the conductor sheet resistance presents a unique problem to designers in simulating circuit behavior.…”
Section: Introductionmentioning
confidence: 99%