Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit

Chong, Soogine; Lee, Byoungil; Parizi, Kokab B.; Provine, J.; Mitra, Subhasish; Howe, Roger T.; Wong, H.-S. Philip

doi:10.1109/iedm.2011.6131645

Cited by 55 publications

(20 citation statements)

References 8 publications

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“…8(b) and (c), the switching speed of a NEM memory switch is lower, and the configuration-mode energy consumption of a NEM memory switch is higher than a MOSFET switch. However, the portion of the configuration mode in the whole operation of an FPGA is very small [3], [22], [23]. On the other hand, the energy consumption in the standby mode of a NEM memory switch is much lower than a MOSFET switch.…”

Section: A Configuration and Standby Operationmentioning

confidence: 99%

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

Kim

Choi

2015

IEEE Trans. Electron Devices

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The application of nanoelectromechanical (NEM) memory switches to field-programmable gate arrays (FPGAs) has been proposed for the first time. NEM memory switches replace MOSFETs and NEM relay switches in connection blocks and switch boxes. The proposed NEM-memory-based FPGAs feature higher speed, lower energy consumption, and smaller chip area than the other FPGAs. In addition, compared with the previously reported NEM-relay-based FPGAs, they show nonvolatile storage of signal paths and stable rail-to-rail signal voltage swing because data signal paths are maintained by adhesion force. In addition, the contact resistance (R co ) of a NEM memory switch is lower than that of a NEM relay switch thanks to larger contact area.Index Terms-Adhesion force, nanoelectromechanical (NEM) memory switch, nonvolatile operation, reconfigurable logic.

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Section: A Configuration and Standby Operationmentioning

confidence: 99%

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

Kim

Choi

2015

IEEE Trans. Electron Devices

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“…Although there have been several studies on CMOS-NEM reconfigurable circuits, most of them only proposed their concepts, showed simulation results or implemented only NEM relays [2]- [7]. Although one previous research implemented CMOS-NEM hybrid circuits, it did not show reconfigurable circuit operation and stable and nonvolatile data signal paths [1].…”

Section: Introductionmentioning

confidence: 97%

“…C OMPLEMENTARY metal-oxide-semiconductor (CMOS)nano-electromechanical (NEM) reconfigurable circuits have some advantages over CMOS-only ones [1]- [7]. First, the former have smaller chip area than the latter because the routing parts using NEM switches are located over CMOS logic parts.…”

Section: Introductionmentioning

confidence: 99%

Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits

Choi

Kim

2015

IEEE Electron Device Lett.

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Complementary-metal-oxide-semiconductor (CMOS) and nanoelectromechanical (NEM) hybrid reconfigurable circuits are implemented for the first time using three-dimensional (3D) integration process. In addition, their operation is confirmed experimentally. For the fabrication of the 3D CMOS-NEM hybrid reconfigurable circuits, only the standard CMOS baseline process has been used except for the hydrofluoric acid vapor etch to release the NEM structures and focused-ion-beam patterning to define small patterns. IndexTerms-Complementary-metal-oxide-semiconductor (CMOS), nano-electromechanical (NEM) memory switch, three-dimensional (3D) integration, reconfigurable cicuit.

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“…In fact, the use of mechanical switches for computing is not a new idea, but dates back to the 1930's [6]. Due to impressive advances in manufacturing techniques and photolithography of bulk-planar processing technology over the past few decades, the interest in the development of surface micromachining processes for micro-and nanoelectromechanical systems (MINEMS) has been renewed for several applications in mechanical computing such as ultra-low power IC applications [7], static random ac cess memories (SRAM) [8], NEM relays integrated in CMOS circuitry [9] and operating in extremely hard conditions [10].…”

Section: Introductionmentioning

confidence: 99%

3-terminal tungsten CMOS-NEM relay

Riverola

Vidal-Álvarez

Torres

et al. 2014

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Ahstract-The present work describes the design, fabrication and experimental results of a 3-terminal laterally actuated tung sten nanoelectromechanical (NEM) relay which is monolithically integrated in a 0.35 J.lm commercial standard CMOS technology. The movable structure is released by means of a simple one-step maskless wet etching. The switch shows an abrupt switching with less than 5 mY/decade and a good on-off current ratio of rv 104 although it exhibits an on-state contact resistance RON around 500 Mn. Also, the relay is cycled up to 1500 times in ambient conditions showing great endurance but variability in its contact.Nowadays we live in a digital era surrounded by plenty of electronic devices that have become a pervasive part of our daily lives, available everywhere and anytime. This fact has been possible thanks to the rapid growth in integrated circuit (lC) technology over the last decades. As we know, the main block of these electronic devices is the IC chip which is generally built using the technology so-called complementary metal oxide semiconductor (CMOS) that uses symmetric pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) to achieve complementary switching behaviour.Basically, the rapid CMOS technology advancement was achieved following simple scaling rules to reduce the dimen sions of the metal oxide semiconductor (MOS) transistors, thus achieving better performance and more integration density, reaching more functionality per chip and reduced cost per area [1]. However, in the deep-submicron regime is increasingly difficult to continue this scaling-down approach: a power crisis has emerged due to a fundamental issue inherent in the MOSFET operating principle [2, 3].The CMOS circuit power dissipation can be expressed as a sum of two power dissipation mechanisms [4]: active power dissipation PA and standby power dissipation Ps which are given bywhere in (1), K is the switching factor, C is the total capacitance and f is the operating clock frequency. In (2), IOFF is the total leakage current. VDD is the applied voltage in both terms.As CMOS is scaled to smaller dimensions and the supply voltage VDD is reduced to maintain reliability and reasonable active power dissipation, the threshold voltage VTH needs to 978-1-4799-4994-6/14/$3l.00 ©20 14 IEEE be scaled down at the same rate as VDD in order to achieve the desired circuit switching speed [4]. However, the supply voltage is not expected to be scaled down further in smaller technology nodes due to the thermal limit kBT/q [5], where kB is the Boltzmann constant, T is the temperature and q is the elementary charge. As a result, the Ps is increasing rapidly becoming the dominant factor in total power dissipation at small channel lengths. Nanoelectromechanical (NEM) relays are proposed to solve the standby power dissipation problem because they have zero leakage current and abrupt ON/OFF transition, since the device can be considered as an ideal switch. In fact, the use of mechanical switches for computing is no...

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Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit

Cited by 55 publications

References 8 publications

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits

3-terminal tungsten CMOS-NEM relay

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