2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers 2014
DOI: 10.1109/vlsit.2014.6894427
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Integration of silicon photonics in bulk CMOS

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Cited by 17 publications
(8 citation statements)
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“…Applicability to CMOS Processes with Bulk Silicon Substrates. CMOS processes utilizing a bulk silicon substrate lack a patternable crystalline silicon layer, motivating alternative devices in polysilicon and a small number of process changes 36 . However, some guiding principles of zerochange integration, such as reuse of existing transistor mask levels, repurposing of transistor materials for optics, and compact integration through silicon microrings, can be applied to minimize changes to the process frontend, which are the most harmful to process-native electronics.…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…Applicability to CMOS Processes with Bulk Silicon Substrates. CMOS processes utilizing a bulk silicon substrate lack a patternable crystalline silicon layer, motivating alternative devices in polysilicon and a small number of process changes 36 . However, some guiding principles of zerochange integration, such as reuse of existing transistor mask levels, repurposing of transistor materials for optics, and compact integration through silicon microrings, can be applied to minimize changes to the process frontend, which are the most harmful to process-native electronics.…”
Section: Methodsmentioning
confidence: 99%
“…However, some guiding principles of zerochange integration, such as reuse of existing transistor mask levels, repurposing of transistor materials for optics, and compact integration through silicon microrings, can be applied to minimize changes to the process frontend, which are the most harmful to process-native electronics. These concepts have been applied successfully in practice to enable functional photonics in bulk 26,36 , though at far smaller scale. Correspondence Correspondence and requests for materials should be addressed to Vladimir Stojanović (email: vlada@berkeley.edu), Miloš Popović (email: milos.popovic@colorado.edu), Rajeev Ram (email: rajeev@mit.edu), or Krste Asanović (email: krste@berkeley.edu).…”
Section: Methodsmentioning
confidence: 99%
“…This means that the quantum efficiency of the present geometry can reach at least 20% in the long-device limit. Furthermore, results in a 0.18 lm bulk CMOS node 20 show that the propagation loss of optimized polysilicon waveguides can be as low as 10 dB/cm. Because of the small optical overlap with the polysilicon rib of the current geometry (Fig.…”
mentioning
confidence: 99%
“…In 2014, the first monolithic integration of photonic and electronic devices on the bulk CMOS was reported [ 49 ]. The most challenging part is the waveguide integration with a low propagation loss.…”
Section: Silicon Photonics For High-speed Data Communicationsmentioning
confidence: 99%
“…A DWDM optical transceiver is monolithically integrated on a 0.18-μm bulk CMOS process with all the optical devices implemented using polysilicon without relying on the epitaxial crystallization of silicon or the introduction of Ge. By applying the same approaches presented in [ 49 ], low-loss photonic devices including waveguides, couplers, micro-ring modulators, and PDs can be successfully integrated with minimal modifications to the original CMOS process. Moreover, based on the micro-ring structures, 9-wavelength TX and RX DWDM macros are also realized as shown in Figure 10 .…”
Section: Silicon Photonics For High-speed Data Communicationsmentioning
confidence: 99%