Intel 870: a building block for cost-effective, scalable servers

Interconnect-Aware Coherence Protocols for Chip Multiprocessors

“…L2 cache latencies are relatively high as a processor core has to acquire the bus before sending a request to L2. It is difficult to support a large number of processor cores with a single bus due to the bandwidth and electrical limits of a centralized bus [11]. In a directory-based design [13,28], each L1 connects to the L2 cache through a point-to-point link.…”

ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers

“…Several previous works [14,43,53,57] examined different physical-to-bank address mapping mechanisms to improve performance obtained from the memory system. Other works [6,37,7,8,26,12,19,3] have examined different memory controller design choices, such as row buffer open/closed policies and power management techniques. All of these mechanisms are orthogonal to memory scheduling and can be applied in conjunction with ATLAS.…”

A study of performance impact of memory controller features in multi-processor server environment

“…In this study we investigate a system with an out-oforder IPF FSB, specifically the single-bus version of the Intel 870 ( [2]). This system consists of an IPF FSB at 200MHz / 400MT/s (6.4GB/s peak BW) and four lock-step 1.6GB/s memory channels connected to the MCH component (named SNC, Scalable Node Controller, in Intel 870).…”